MAX5774EVKIT+ Maxim Integrated Products, MAX5774EVKIT+ Datasheet - Page 9

• Manufacturer Part Number: MAX5774EVKIT+
• Description: KIT EVAL FOR MAX5774
• Manufacturer: Maxim Integrated Products

Specifications of MAX5774EVKIT+

• Number Of Dac's: 32
• Number Of Bits: 14
• Outputs And Type: 32, Single Ended
• Data Interface: Serial
• Settling Time: 20µs
• Dac Type: Voltage
• Voltage Supply Source: Analog and Digital
• Operating Temperature: 0°C ~ 85°C
• Utilized Ic / Part: MAX5774
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

TIMING CHARACTERISTICS
(Figures 1 and 2, AV
T
TIMING CHARACTERISTICS (continued)
(Figures 1 and 2, AV
T
Note 1: AV
Note 2: Linearity guaranteed for full code range.
Note 3: Offset error is measured at code 0. Gain error is measured at code 3FFFh.
Note 4: DC crosstalk is the change in the output level of one DAC at midscale in response to the full-scale output change of all other DACs.
Note 5: Digital feedthrough is a measure of the impulse injected into the analog outputs from the digital control inputs when the
Note 6: DAC-to-DAC crosstalk is the glitch impulse that appears at the output of one converter due to both the digital change and
Note 7: In DSP mode, maintain the maximum CS pulse width low to ≤ 16 SCLK cycles.
MAX
Serial Clock Frequency
SCLK Pulse-Width High
SCLK Pulse-Width Low
SCLK Fall to CS Fall Setup Time
CS Fall to SCLK Fall Setup Time
CS Rise to SCLK Fall
SCLK Fall to CS Rise Setup Time
DIN to SCLK Fall Setup Time
DIN to SCLK Fall Hold Time
SCLK Fall to DOUT Fall
SCLK Fall to DOUT Rise
CS Pulse-Width High
CS Pulse-Width Low
LDAC Pulse-Width Low
RESET Pulse-Width Low
MAX
CS Fall to SCLK Fall Setup Time
CS Rise to SCLK Fall
SCLK Fall to CS Rise Setup Time
DIN to SCLK Fall Setup Time
DIN to SCLK Fall Hold Time
SCLK Fall to DOUT Fall
SCLK Fall to DOUT Rise
CS Pulse-Width High
CS Pulse-Width Low
LDAC Pulse-Width Low
RESET Pulse-Width Low
, unless otherwise noted. Typical values are at T
, unless otherwise noted. Typical values are at T
device is not being written to. It is measured with a worst-case change on the digital inputs.
subsequent analog output change at another converter.
PARAMETER
PARAMETER
CC
should be at least 0.25V higher than the maximum output voltage required from the DAC.
DD
DD
_______________________________________________________________________________________
= +4.75V to +5.25V, DV
= +4.75V to +5.25V, DV
32-Channel, 14-Bit, Voltage-Output
SYMBOL
SYMBOL
t
t
t
t
CSPWH
CSPWH
CSPWL
CSPWL
t
t
f
SCLK
t
t
t
LDAC
t
t
t
LDAC
t
t
t
t
t
t
t
t
t
t
t
SCS
CSS
t
SDH
CLR
CSS
t
SDH
CLR
CS1
CS2
SCL
CS1
CS2
SCL
CH
DH
DH
CL
DS
DS
DD
DD
At end of cycle in SPI mode only
Load capacitance = 20pF
Load capacitance = 20pF
(Note 7)
At end of cycle in SPI mode only
Load capacitance = 20pF
Load capacitance = 20pF
(Note 7)
= +4.75V to +5.25V, AGND = DGND = REFGND = GS1 = GS2 = 0, T
= +2.7V to +5.25V, AGND = DGND = REFGND = GS1 = GS2 = 0, T
A
A
= +25°C.)
= +25°C.)
DACs with Serial Interface
CONDITIONS
CONDITIONS
MIN
MIN
10
10
10
10
18
10
50
20
20
50
15
10
50
20
20
50
0
0
2
5
0
2
TYP
TYP
MAX
MAX
25
25
25
20
20
A
A
= T
= T
UNITS
UNITS
MHz
MIN
MIN
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
to
to
9