LP5900TL-2.0EV National Semiconductor, LP5900TL-2.0EV Datasheet

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LP5900TL-2.0EV

Manufacturer Part Number
LP5900TL-2.0EV
Description
BOARD EVALUATION LP5900TL-2.0
Manufacturer
National Semiconductor
Datasheets

Specifications of LP5900TL-2.0EV

Channels Per Ic
1 - Single
Voltage - Output
2V
Current - Output
150mA
Voltage - Input
2.5 ~ 5.5V
Regulator Type
Positive Fixed
Operating Temperature
-40°C ~ 125°C
Board Type
Fully Populated
Utilized Ic / Part
LP5900
Lead Free Status / RoHS Status
Not applicable / Not applicable
© 2007 National Semiconductor Corporation
LP5900 microSMD
Evaluation Board
Information
Introduction
This evaluation board is designed to enable the evaluation of
the LP5900 Voltage Regulator. Each board is assembled and
tested in the factory. This evaluation board has the microS-
MD-4 bump package mounted.
General Description
The LP5900 is a linear regulator capable of suppling 150mA
output current. Designed to meet the requirements of RF/
Analog circuits, the LP5900 provides low device noise, high
PSRR, low quiescent current, and low line transient response.
Using new innovative design techniques the LP5900 offers
class-leading noise performance without a noise bypass ca-
pacitor.
The device has been designed to work with 0.47µF input and
output ceramic capacitors down to 0603 component size.
Schematic Diagram
201649
Evaluation Board Schematic.
National Semiconductor
Application Note 1396
John Bowie
September 2007
Operation
The input voltage, applied between V
at least 1.0V greater than V
minimum operating voltage is 2.5V. Loads can be connected
to V
provided on the board to allow accurate measurements di-
rectly onto the input and output pins of the device, eliminating
any voltage drop on the PCB traces or connecting wires to the
load.
ON/OFF control is provided by a logic signal on the V
A minimun of 1.2V is required at this pin to enable the LDO.
The LDO will be shutdown when the V
less.
In applications were the LP5900 is operated continuously
from the battery then V
ever if ON/OFF control is required the V
driven from a seperate signal to ensure correct operation of
the fast start-up circuit. The device has a 1MΩ internal resistor
from V
Hardware
The schematic and layout of the evaluation board are given
below:
OUT
EN
with reference to GND. V
to GND.
IN
and V
OUT
EN
and no more than 5.5V. The
OUT
can be tied together. How-
and V
IN
EN
20164904
and GND, should be
pin is set to 0.4V or
EN
IN
sense pins are
pin should be
www.national.com
EN
pin.

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LP5900TL-2.0EV Summary of contents

Page 1

... The device has been designed to work with 0.47µF input and output ceramic capacitors down to 0603 component size. Schematic Diagram © 2007 National Semiconductor Corporation National Semiconductor Application Note 1396 John Bowie September 2007 ...

Page 2

... PCB Layout Evaluation Board Component and Pin Layout Board Size:- 21mm x 21mm Hardware Designator U1 LP5900TL CIN 0.47µF COUT 0.47µF IN, OUT, IN SENSE, OUT SENSE, ON/OFF, Test Pins GND www.national.com Value Amount 20164910 Footprint Note TLA4CDA 0603 X7R, X5R 0603 X7R, X5R ...

Page 3

Notes 3 www.national.com ...

Page 4

... National Semiconductor and the National Semiconductor logo are registered trademarks of National Semiconductor Corporation. All other brand or product names may be trademarks or registered trademarks of their respective holders. ...

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