AD8250-EVALZ Analog Devices Inc, AD8250-EVALZ Datasheet - Page 2

• Manufacturer Part Number: AD8250-EVALZ
• Description: BOARD EVALUATION AD8250
• Manufacturer: Analog Devices Inc
• Series: iCMOS®r

Specifications of AD8250-EVALZ

• Channels Per Ic: 1 - Single
• Amplifier Type: Instrumentation
• Output Type: Single-Ended
• Slew Rate: 25 V/µs
• -3db Bandwidth: 10MHz
• Current - Output / Channel: 37mA
• Operating Temperature: -40°C ~ 85°C
• Current - Supply (main Ic): 4.1mA
• Voltage - Supply, Single/dual (±): 10 V ~ 30 V, ±5 V ~ 15 V
• Board Type: Fully Populated
• Utilized Ic / Part: AD8250
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD8250-EVALZ
EVALUATION BOARD HARDWARE
QUICK START GUIDE
By default, the AD8250-EVALZ is configured for gain change
using the on-board switches, SW1 and SW2, as shown in Table 1.
Table 1. Gain Setting Using the On-Board Switches
W3 (Jumper)
In place
In place
In place
In place
Table 2. Default Settings (From the Factory)
Name
W1, W2, W3
JP1, JP3, R1, R2, R3, R5
USING EXTERNAL LOGIC TO CHANGE GAIN
The AD8250-EVALZ accepts external logic signals such as
those from logic generators or FPGAs. To change gains using
external logic signals, Jumpers W1, W2, and W3 must be
removed. Only then will the A0, A1, and WR pins on the
AD8250 be directly tied to TP3, TP4, and TP5 (and to the
respective SMA connectors). External logic can be tied via the
test points TP3, TP4 and TP5, or via the respective SMA
connector.
TERMINATION
The AD8250-EVALZ has 50 Ω traces leading to the A0, A1, and
WR pins. However, it does not have terminations to those pins.
If terminations are added, remove Jumper W1, Jumper W2, and
Jumper W3.
RFI FILTER
An RFI filter pattern is included at the input traces of the
AD8250-EVALZ. R1 and R2 are shorted. The shorted traces
must be cut before R1 and R2 are placed on the board.
OUTPUT FILTER
An output filter pattern is included at the output trace of the
AD8250-EVALZ. To use R3 or R5 in a filter, cut the shorted
traces prior to placing resistors in those locations.
REFERENCE
To level shift the output, a nonzero reference voltage can be applied
to REF. By default, REF is tied to analog GND. Cutting the trace
at JP1 opens the connection between REF and analog GND.
ANALOG AND DIGITAL GROUND
Analog and digital grounds are tied at JP3. To sever the
connection between them, JP3 can be cut with a knife to open
the connection between the two grounds.
SW2
Low
Low
High
High
Default Status
In place (tied)
Shorted by design (on trace)
SW1
Low
High
Low
High
Gain
1
2
5
10
Rev. 0 | Page 2 of 4
GAIN SELECTION (FROM AD8250 DATA SHEET)
This section shows users how to configure the AD8250 for basic
operation. Logic low and logic high voltage limits are listed in
the Specifications section of the
logic low is 0 V and logic high is 5 V; both voltages are meas-
ured with respect to DGND. Refer to the specifications table of
the AD8250 for the permissible voltage range of DGND. The
gain of the AD8250 can be set using two methods.
Transparent Gain Mode
The easiest way to set the gain is to program it directly via a
logic high or logic low voltage applied to A0 and A1. Figure 2
shows an example of this gain setting method, referred to through-
out the data sheet as transparent gain mode. Tie WR to the
negative supply to engage transparent gain mode. (On the
AD8250-EVALZ board, put the W3 jumper in place.) In this
mode, any change in voltage applied to A0 and A1 from logic
low to logic high, or vice versa, immediately results in a gain
change. Table 3 is the truth table for transparent gain mode and
Figure 2 shows the AD8250 configured in transparent gain mode.
Table 3. Truth Table Logic Levels for Transparent Gain Mode
WR (W3)
−V
−V
−V
−V
S
S
S
S
(in place)
(in place)
(in place)
(in place)
Figure 2. Transparent Gain Mode, A0 and A1 = High, G = 10
NOTE:
1. IN TRANSPARENT GAIN MODE, WR IS TIED TO −V
THE VOLTAGE LEVELS ON A0 AND A1 DETERMINE
THE GAIN. IN THIS EXAMPLE, BOTH A0 AND A1 ARE
SET TO LOGIC HIGH, RESULTING IN A GAIN OF 10.
–IN
+IN
10μF
10μF
A1 (SW2)
Low
Low
High
High
0.1µF
0.1µF
+15V
–15V
AD8250
DGND
WR
A0 (SW1)
Low
High
Low
High
AD8250
A1
A0
REF
DGND
data sheet. Typically,
–15V
+5V
+5V
G = 10
Gain
1
2
5
10
S
.