STEVAL-MKI030V1 STMicroelectronics, STEVAL-MKI030V1 Datasheet
STEVAL-MKI030V1
Specifications of STEVAL-MKI030V1
Related parts for STEVAL-MKI030V1
STEVAL-MKI030V1 Summary of contents
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Features ■ Wide supply voltage, 2. 3.6 V ■ Low voltage compatible IOs, 1.8 V ■ Ultra low-power mode consumption down to 10 µA ±2g/±4g/±8g dynamically selectable full-scale ■ 2 ■ ...
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Contents Contents 1 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.1 Block ...
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LIS331DLH 6 Register mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of tables List of tables Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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LIS331DLH Table 49. INT2_SRC register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of figures List of figures Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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LIS331DLH 1 Block diagram and pin description 1.1 Block diagram Figure 1. Block diagram a SELF TEST 1.2 Pin description Figure 2. Pin connection X Y (TOP VIEW) DIRECTION OF THE DETECTABLE ACCELERATIONS X+ Y+ CHARGE AMPLIFIER Z+ A/D MUX ...
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Block diagram and pin description Table 2. Pin description Pin 8/38 Name Vdd_IO Power supply for I/O pins NC Not connected NC Not connected ...
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LIS331DLH 2 Mechanical and electrical specifications 2.1 Mechanical characteristics Table 3. Mechanical characteristics @ Vdd = 2 °C unless otherwise noted Symbol Parameter FS Measurement range So Sensitivity Sensitivity change vs TCSo temperature g Typical zero- ...
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Mechanical and electrical specifications 2.2 Electrical characteristics Table 4. Electrical characteristics @ Vdd = 2 °C unless otherwise noted Symbol Parameter Vdd Supply voltage Vdd_IO I/O pins supply voltage Current consumption Idd in normal mode Current ...
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LIS331DLH 2.3 Communication interface characteristics 2.3.1 SPI - serial peripheral interface Subject to general operating conditions for Vdd and Top. Table 5. SPI slave timing values Symbol tc(SPC) SPI clock cycle fc(SPC) SPI clock frequency tsu(CS) CS setup time th(CS) ...
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Mechanical and electrical specifications 2 2.3 inter IC control interface Subject to general operating conditions for Vdd and top. 2 Table slave timing values Symbol Parameter f SCL clock frequency (SCL) t SCL clock ...
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LIS331DLH 2.4 Absolute maximum ratings Stresses above those listed as “absolute maximum ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these conditions is not implied. Exposure to ...
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Mechanical and electrical specifications 2.5 Terminology 2.5.1 Sensitivity Sensitivity describes the gain of the sensor and can be determined e.g. by applying 1 g acceleration to it. As the sensor can measure DC accelerations this can be done easily by ...
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LIS331DLH 3 Functionality The LIS331DLH is a “nano”, low-power, digital output 3-axis linear accelerometer packaged in a LGA package. The complete device includes a sensing element and an IC interface able to take the information from the sensing element and ...
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Application hints 4 Application hints Figure 5. LIS331DLH electrical connection Vdd Digital signal from/to signal controller.Signal’s levels are defined by proper selection of Vdd_IO The device core is supplied through Vdd line while the I/O pads are supplied through Vdd_IO ...
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LIS331DLH 5 Digital interfaces The registers embedded inside the LIS331DLH may be accessed through both the I SPI serial interfaces. The latter may be SW configured to operate either in 3-wire or 4-wire interface mode. The serial interfaces are mapped ...
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Digital interfaces 2 5.1 operation The transaction on the bus is started through a START (ST) signal. A START condition is defined as a HIGH to LOW transition on the data line while the SCL line is held ...
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LIS331DLH Table 12. Transfer when master is writing multiple bytes to slave: Master ST Slave Table 13. Transfer when master is receiving (reading) one byte of data from slave: Master ST SAD + W Slave Table 14. Transfer when Master ...
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Digital interfaces Figure 6. Read and write protocol CS SPC SDI SDO CS is the serial port enable and it is controlled by the SPI master. It goes low at the start of the transmission and goes back high at ...
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LIS331DLH The SPI Read command is performed with 16 clock pulses. Multiple byte read command is performed adding blocks of 8 clock pulses at the previous one. bit 0: READ bit. The value is 1. bit 1: MS bit. When ...
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Digital interfaces Figure 10. Multiple bytes SPI write protocol (2 bytes example) CS SPC SDI RW MS 5.2.3 SPI read in 3-wires mode 3-wires mode is entered by setting to ‘1’ bit SIM (SPI serial interface mode selection) in CTRL_REG4. ...
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LIS331DLH 6 Register mapping The table given below provides a listing of the 8 bit registers embedded in the device and the related addresses: Table 15. Register address map Name Reserved (do not modify) WHO_AM_I Reserved (do not modify) CTRL_REG1 ...
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Register mapping The content of the registers that are loaded at boot should not be changed. They contain the factory calibration values. Their content is automatically restored when the device is powered-up. 24/38 Doc ID 15094 Rev 3 LIS331DLH ...
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LIS331DLH 7 Register description The device contains a set of registers which are used to control its behavior and to retrieve acceleration data. The registers address, made of 7 bits, is used to identify them and to write the data ...
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Register description Table 19. Power mode and low-power output data rate configurations PM2 PM1 Table 20. Normal-mode output data rate configurations and low-pass cut-off frequencies DR1 7.3 CTRL_REG2 (21h) ...
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LIS331DLH Table 22. CTRL_REG2 description (continued) High pass filter enabled for interrupt 1 source. Default value: 0 HPen1 (0: filter bypassed; 1: filter enabled) High pass filter cut-off frequency configuration. Default value: 00 HPCF1, HPCF0 (00: HPc=8; 01: HPc=16; 10: ...
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Register description 7.4 CTRL_REG3 [Interrupt CTRL register] (22h) Table 25. CTRL_REG3 register IHL PP_OD Table 26. CTRL_REG3 description Interrupt active high, low. Default value: 0 IHL (0: active high; 1:active low) Push-pull/Open drain selection on interrupt pad. Default value 0. ...
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LIS331DLH Table 29. CTRL_REG4 description (continued) Full-scale selection. Default value: 00. FS1, FS0 (00: ±2 g; 01: ±4 g; 11: ±8 g) Self-test sign. Default value: 00. STsign (0: self-test plus; 1 self-test minus) Self-test enable. Default value ...
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Register description 7.7 HP_FILTER_RESET (25h) Dummy register. Reading at this address zeroes instantaneously the content of the internal high pass-filter. If the high pass filter is enabled all three axes are instantaneously set to 0g. This allows to overcome the ...
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LIS331DLH Table 36. STATUS_REG description (continued) ZDA Z axis new data available. Default value: 0 (0: a new data for the Z-axis is not yet available new data for the Z-axis is available) YDA Y axis new data ...
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Register description Table 38. INT1_CFG description Enable interrupt generation on Y low event. Default value: 0 YLIE (0: disable interrupt request; 1: enable interrupt request on measured accel. value lower than preset threshold) Enable interrupt generation on X high event. ...
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LIS331DLH Interrupt 1 source register. Read only register. Reading at this address clears INT1_SRC IA bit (and the interrupt signal on INT 1 pin) and allows the refreshment of data in the INT1_SRC register if the latched option was chosen. ...
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Register description Table 47. INT2_CFG description (continued) Enable interrupt generation on Y high event. Default value: 0 YHIE (0: disable interrupt request; 1: enable interrupt request on measured accel. value higher than preset threshold) Enable interrupt generation on Y low ...
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LIS331DLH Table 50. INT2_SRC description X high. Default value (0: no interrupt high event has occurred) X Low. Default value (0: no interrupt low event has occurred) Interrupt 2 source register. Read ...
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Package information 8 Package information In order to meet environmental requirements, ST offers these devices in different grades of ® ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ...
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LIS331DLH 9 Revision history Table 55. Document revision history Date 16-Oct-2008 21-Nov-2008 10-Jul-2009 Revision 1 Initial release Table 3 on page 9 2 Updated Table 4 on page 10 Updated: 3 Minor text changes to improve readability Doc ID 15094 ...
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