EZ80F917050SBCG Zilog, EZ80F917050SBCG Datasheet - Page 15

• Manufacturer Part Number: EZ80F917050SBCG
• Description: BOARD ZDOTS SBC Z80ACCLAIM PLUS
• Manufacturer: Zilog
• Series: Zdots® SBCr
• Type: MCUr

Specifications of EZ80F917050SBCG

• Contents: Fully Assembled Evaluation Board
• For Use With/related Products: eZ80F91
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4671

PS026102-1207
Table 2. Zdots Input/Output Connector Pin Identification* (Continued)
Pin No
57
58
59
60
*Notes
1. External capacitive loads on RD, WR, IORQ, MREQ, D0–D7, and A0–A23 must be below 10 pF to satisfy
2. All unused inputs must be pulled to either V
3. All inputs are CMOS level 3.3 V (5 V tolerant), except where otherwise noted.
consumption and to reduce noise sensitivity.
timing requirements for the CPU.
Symbol
HALT_SLP
NMI
V
Reserved
CC
Pull
Up/Down
PU 10 k
Ω
Signal
Direction
Output, Active
Low
Schmitt-trigger
Input, Active
Low
NC
Zdots
DD
®
SBC for eZ80AcclaimPlus!
or GND, depending on their inactive levels, to reduce power
Comments
A Low on this pin indicates that the CPU enters
either HALT or SLEEP mode because of
execution of either a HALT or SLP instruction.
The NMI input is a higher priority input than the
maskable interrupts. It is always recognized at
the end of an instruction, regardless of the state
of the interrupt enable control bits. This input
includes a Schmitt-trigger to allow RC rise times.
This external NMI signal is combined with an
internal NMI signal generated from the WDT
block before being connected to the NMI input of
the CPU.
3.3 V supply input pin.
Reserved—No Connection.
Product Specification
™
Connectivity ASSP
Pin Description
11