Z8F04A08100KITG Zilog, Z8F04A08100KITG Datasheet - Page 24

• Manufacturer Part Number: Z8F04A08100KITG
• Description: KIT DEV Z8 ENCORE XP 8-PIN
• Manufacturer: Zilog
• Series: Z8 Encore! XP®r
• Type: MCUr

Specifications of Z8F04A08100KITG

• Contents: Hardware, Software and Documentation
• For Use With/related Products: Z8 Encore! XP 8-pin
• For Use With: 269-4661 - KIT ACC ETHERNET SMART CABLE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4628

UM018702-0505
VCC_33V
GND
R16
0
C10
R19
0
PA1_JP
R17
0
Clock Mode
Internal
Ceramic Res
Crystal
PA0_JP
1
Y1
1
TABLE 1
VCC_33V
VCC_33V
VCC_33V
VCC_33V
VCC_33V
VCC_33V
VCC_33V
20 MHz
1
220K
PA0
PA1
PA2_JP
R21
3
TEST
S1
3
Schematic, Z8 Encore! XP™ 4K Series 8-Pin MCU Development Board, Page 2 of 2
Note 2
R16
none
none
2
1
2
3
4
8 pin footprint
C11
Z8F04xA_8pin
R20
0
U5
VDD
PA0
PA1
PA2
R12
10K
Note 2
PA3_CTS0
NOTE 2
R17
none
none
C13
VSS
PA5
PA4
PA3
0 Ohm
0 Ohm
8
7
6
5
R19
none
PA5_JP
PA4_JP
PA3_JP
GND
0 Ohm
0 Ohm
R20
none
R11
100
R13
100
R15
100
R21
none
220K 10-20pF
220K 10-20 pF 10-20 pF
PA3_CTS0
PA4_RXD0
2
2
2
PA5_TXD0
D2
LED
D3
LED
D4
LED
C10
none
GREEN
YEL
RED
1
1
1
PA3_CTS0
PA4_RXD0
PA5_TXD0
C11
none
10-20pF
LED_G
LED_Y
LED_R
DEMO
DEMO
DEMO
DEMO
DEMO
DEMO
PA0_JP
PA1_JP
PA2_JP
PA3_JP
PA4_JP
PA5_JP
Y1
none
select
select
Header 3
Header 3
Header 3
Header 3
Header 3
Header 3
user
user
PA0
PA1
PA2
J3
J5
J6
J8
PA3
J9
PA4
J10
PA5
J4
HEADER 2
PA0_MDS
USER
PA1_MDS
USER
PA2_MDS
USER
PA3_MDS
USER
PA4_MDS
USER
PA5_MDS
USER
1
2
Note 2:
The XP supports internal oscillator, external crystal, or ceramic
resonator, external R/C and external CMOS drive clock
R17, R19, R20, R21, C10, C11 and Y1 are used to support the clock
selected. The development board is shipped configured for
oscillator. When
as GPIO ports PA0 and
configurations.
J7
HEADER 2
1
2
RESET
DBG
using
DBG
PA1. Table 1 shows the recommended clock mode
internal
oscilator, pins 2 and 3 could be used
GND
RESET
-RESET
SW1
Note 1:
If Module is plugged onto the Dev Platform the local
RS232 interface is disabled by pin 50 of JP2
VCC_33V
modes.
internal
R16,
R14
10K
mode
Title
Size
Date:
B
XP 4K 8pin MDS Processor Module. Schematic.
Document Number
VCC_33V
PA3_MDS
PA4_MDS
-RESET
-RESET
Tuesday, December 14, 2004
GND
GND
VCC_33V
VCC_33V
GND
GND
-TRSTN
-CS2
GND
A21
A22
-CS0
-BUSACK
Connector JP1
for reference
only
-F91_WE
A6
A10
A8
A13
A15
A18
A19
A2
A11
A4
A5
D1
D3
D5
D7
-MREQ
-WR
96C0964-001
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
1
3
5
7
9
JP2
HEADER 30x2/SM
HEADER 30x2/SM
JP1
connector 2
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
Sheet
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
-DIS_IrDA
VCC_33V
VCC_33V
-DIS_FLASH
VCC_33V
A0
A3
A14
A16
A23
-CS1
GND
A7
A9
A17
D0
D2
D4
D6
-IOREQ
-RD
-INSTRD
-BUSREQ
GND
PA0_MDS
PA1_MDS
PA2_MDS
PA5_MDS
GND
A1
A12
A20
User Manual
GND
2
GND
GND
of
-DIS_232
-DIS_IRDA
2
Rev
B
18