C8051F300-TB Silicon Laboratories Inc, C8051F300-TB Datasheet - Page 114

• Manufacturer Part Number: C8051F300-TB
• Description: BOARD PROTOTYPING W/C8051F300
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F300-TB

• Contents: Board
• Data Bus Width: 8 bit
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: C8051F300
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

C8051F300/1/2/3/4/5
13.3.2. Clock Low Extension
2
SMBus provides a clock synchronization mechanism, similar to I
C, which allows devices with different
speed capabilities to coexist on the bus. A clock-low extension is used during a transfer in order to allow
slower slave devices to communicate with faster masters. The slave may temporarily hold the SCL line
LOW to extend the clock low period, effectively decreasing the serial clock frequency.
13.3.3. SCL Low Timeout
If the SCL line is held low by a slave device on the bus, no further communication is possible. Furthermore,
the master cannot force the SCL line high to correct the error condition. To solve this problem, the SMBus
protocol specifies that devices participating in a transfer must detect any clock cycle held low longer than
25 ms as a “timeout” condition. Devices that have detected the timeout condition must reset the communi-
cation no later than 10 ms after detecting the timeout condition.
When the SMBTOE bit in SMB0CF is set, Timer 2 is used to detect SCL low timeouts. Timer 2 is forced to
reload when SCL is high, and allowed to count when SCL is low. With Timer 2 enabled and configured to
overflow after 25 ms (and SMBTOE set), the Timer 2 interrupt service routine can be used to reset (disable
and reenable) the SMBus in the event of an SCL low timeout. Timer 2 configuration details can be found in
Section “15.2. Timer 2” on page
151.
13.3.4. SCL High (SMBus Free) Timeout
The SMBus specification stipulates that if the SCL and SDA lines remain high for more that 50 µs, the bus
is designated as free. When the SMBFTE bit in SMB0CF is set, the bus will be considered free if SCL and
SDA remain high for more than 10 SMBus clock source periods. If the SMBus is waiting to generate a
Master START, the START will be generated following this timeout. Note that a clock source is required for
free timeout detection, even in a slave-only implementation.
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