C8051F540-TB Silicon Laboratories Inc, C8051F540-TB Datasheet - Page 166
![BOARD PROTOTYPE W/C8051F540](/photos/9/25/92559/c8051f540-tb_sml.jpg)
C8051F540-TB
Manufacturer Part Number
C8051F540-TB
Description
BOARD PROTOTYPE W/C8051F540
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Specifications of C8051F540-TB
Contents
Board
Processor To Be Evaluated
C8051F54x
Processor Series
C8051F54x
Interface Type
USB
Operating Supply Voltage
5 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
C8051F54x
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1672
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C8051F54x
SFR Definition 18.21. P2MDIN: Port 2 Input Mode
SFR Address = 0xF3; SFR Page = 0x0F
SFR Definition 18.22. P2MDOUT: Port 2 Output Mode
SFR Address = 0xA6; SFR Page = 0x0F
166
Note: P2.2-P2.7 are only available on the 32-pin packages.
Note: P2.2-P2.7 are only available on the 32-pin packages.
Name
Reset
Name
Reset
7:0
7:0 P2MDOUT[7:0] Output Configuration Bits for P2.7–P2.0 (respectively).
Bit
Bit
Type
Type
Bit
Bit
P2MDIN[7:0]
Name
Name
7
1
7
0
Analog Configuration Bits for P2.7–P2.0 (respectively).
Port pins configured for analog mode have their weak pull-up and digital receiver
disabled. For analog mode, the pin also needs to be configured for open-drain
mode in the P2MDOUT register.
0: Corresponding P2.n pin is configured for analog mode.
1: Corresponding P2.n pin is not configured for analog mode.
These bits are ignored if the corresponding bit in register P2MDIN is logic 0.
0: Corresponding P2.n Output is open-drain.
1: Corresponding P2.n Output is push-pull.
6
1
6
0
5
1
5
0
Rev. 1.1
P2MDOUT[7:0]
4
1
4
0
P2MDIN[7:0]
R/W
R/W
Function
Function
3
1
3
0
2
1
2
0
1
1
1
0
0
1
0
0
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