COP8SG-EPU National Semiconductor, COP8SG-EPU Datasheet - Page 25

• Manufacturer Part Number: COP8SG-EPU
• Description: BOARD PROTOTYPE/TARGET COP8
• Manufacturer: National Semiconductor
• Type: MCUr

Specifications of COP8SG-EPU

• Contents: *
• For Use With/related Products: Cop 8
• For Use With: COP8SG-EPU - BOARD PROTOTYPE/TARGET COP8
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

USART
USART CONTROL AND STATUS REGISTERS
The operation of the USART is programmed through three
registers: ENU, ENUR and ENUI.
DESCRIPTION OF USART REGISTER BITS
ENU-USART Control and Status Register (Address at 0BA)
PEN: This bit enables/disables Parity (7- and 8-bit modes
only). Read/Write, cleared on reset.
PEN = 0
Bit 7
PEN
PSEL1 XBIT9/
Parity disabled.
(Continued)
PSEL0
CHL1
CHL0
ERR
FIGURE 12. USART Block Diagram
RBFL
TBMT
Bit 0
25
PEN = 1
PSEL1, PSEL0: Parity select bits. Read/Write, cleared on
reset.
PSEL1 = 0, PSEL0 = 0
PSEL1 = 0, PSEL0 = 1
PSEL1 = 1, PSEL0 = 0
PSEL1 = 1, PSEL0 = 1
XBIT9/PSEL0: Programs the ninth bit for transmission when
the USART is operating with nine data bits per frame. For
seven or eight data bits per frame, this bit in conjunction with
PSEL1 selects parity. Read/Write, cleared on reset.
Parity enabled.
Odd Parity (if Parity enabled)
Even Parity (if Parity enabled)
Mark(1) (if Parity enabled)
Space(0) (if Parity enabled)
DS012829-14
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