HW-V5-ML507-UNI-G Xilinx Inc, HW-V5-ML507-UNI-G Datasheet - Page 46

• Manufacturer Part Number: HW-V5-ML507-UNI-G
• Description: EVAL PLATFORM V5 FXT
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 FXTr
• Type: FPGAr

Specifications of HW-V5-ML507-UNI-G

• Contents: ML507 Platform, DVI adapter, CompactFlash Card and SATA Cross-Over Cable
• Silicon Manufacturer: Xilinx
• Features: JTAG Programming Interface, Platform Flash, External Clocking
• Kit Contents: Board
• Silicon Family Name: Virtex-5
• Silicon Core Number: XC5VFX70TFFG1136
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: ML507
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Chapter 1: ML505/ML506/ML507 Evaluation Platform
46
43. GTP/GTX Clocking Circuitry
Overview
Frequency Synthesizer for SFP/SMA GTP/GTX Transceiver Clocking
Low jitter LVDS clock sources on the board provide high-quality reference clocks for the
GTP/GTX transceivers. Different clock sources are provided to support each of the
transceiver interfaces on the board.
sources.
Table 1-29: GTP Clock Sources (ML505/ML506)
Table 1-30: GTX Clock Sources (ML507)
An Integrated Circuit Systems ICS843001-21 frequency synthesizer chip offers flexible,
low-jitter clock generation for the GTP/GTX pair connected to SFP and SMA interfaces.
The ICS843001-21 is connected to a 19.44-MHz crystal and a socketed 25-MHz oscillator
(X5).
DIP switches (SW6) enable the user to select clock source and frequency synthesis options
to generate a number of commonly used frequencies for applications, such as Gigabit
Ethern et and SONET (see
ICS843001-21 data sheet for more information. The 25-MHz oscillator is socketed to allow
the user to change the oscillator frequency and use the entire range of possible synthesized
frequency outputs.
Notes:
1. Driven by an external PCIe source through the PCIe edge connector (P21); not driven internally.
Notes:
1. Driven by an external PCIe source through the PCIe edge connector (P21); not driven internally.
PCIe
PCIe
SATA1
SATA1
SGMII
SGMII
GTP0
GTX0
SFP
SFP
GTP Pairs
GTX Pairs
(1)
(1)
Table 1-29
Loopback
Loopback
Loopback
Loopback
SATA2
SATA2
GTP1
GTX1
SMA
SMA
provides a summary of the GTX clock sources.
www.xilinx.com
Table 1-31, page
75 or 150 MHz
75 or 150 MHz
Frequency
Frequency
125 MHz
100 MHz
125 MHz
100 MHz
Variable
Variable
Table 1-29
47). For other frequencies, consult the
GTP_X0Y2
GTP_X0Y3
GTX_X0Y5
GTX_X0Y3
GTX_X0Y4
GTX_X0Y2
GTP_X0Y4
GTP_X0Y1
Location
Location
GTP Tile
GTX Tile
provides a summary of the GTP clock
ML505/ML506/ML507 Evaluation Platform
UG347 (v3.1.1) October 7, 2009
Positive
Positive
GTP REFCLK Diff Pair
GTX REFCLK Diff Pair
AF4
AF4
H4
H4
Y4
Y4
P4
P4
Negative
Negative
AF3
AF3
H3
H3
Y3
P3
Y3
P3
R