HW-V5-ML506-UNI-G Xilinx Inc, HW-V5-ML506-UNI-G Datasheet - Page 45

• Manufacturer Part Number: HW-V5-ML506-UNI-G
• Description: EVALUATION PLATFORM VIRTEX-5
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 SXTr
• Type: DSPr

Specifications of HW-V5-ML506-UNI-G

• Contents: Evaluation Platform, DVI Adapter and CompactFlash Card
• Silicon Manufacturer: Xilinx
• Features: JTAG Programming Interface, Platform Flash, External Clocking
• Kit Contents: Board, Cable, PSU, CD, Docs
• Silicon Family Name: Virtex-5
• Silicon Core Number: XC5VSX50TFFG1136
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: XC5VSX50TFFG1136
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

ML505/ML506/ML507 Evaluation Platform
UG347 (v3.1.1) October 7, 2009
R
Table 1-27: Configuration for SFP Module Control and Status Signals
Table 1-28: SFP Module Connections
SFP TX FAULT
SFP TX DISABLE
SFP MOD DETECT
SFP RT SEL
SFP LOS
CLKBUF_Q0_P
CLKBUF_Q0_N
SFP_RX_P
SFP_RX_N
SFP_TX_P
SFP_TX_N
SFP Control/Status Signal
SFP Signal
FPGA Pin (U1)
H4
H3
H1
www.xilinx.com
G1
G2
F2
Test Point TP20
• High = Fault
• Low = Normal Operation
Jumper J82
• Jumper Off = SFP Enabled
• Jumper On = SFP Disabled
Test Point TP21
• High = Module Not Present
• Low = Module Present
Jumper J81
• Jumper Off = Full Bandwidth
• Jumper On = Reduced Bandwidth
Test Point TP22
• High = Loss of Receiver Signal
• Low = Normal Operation
LED DS40
• LED Off = Loss of Receiver Signal
• LED On = Normal Operation
AC-coupled, LVDS, GTP REFCLK pair.
• ML505/ML506: GTP0 of GTP_X0Y4
• ML507: GTX0 of
Transmit pair.
• ML505/ML506: GTP0 of GTP_X0Y4
• ML507: GTX0 of
Receive pair.
Board Connection
GTX_X0Y5
GTX_X0Y5
Description
Detailed Description
45