HW-V5-PCIE2-UNI-G Xilinx Inc, HW-V5-PCIE2-UNI-G Datasheet - Page 76
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HW-V5-PCIE2-UNI-G
Manufacturer Part Number
HW-V5-PCIE2-UNI-G
Description
KIT DEV PCIEXPRESS GTX VIRTEX5
Manufacturer
Xilinx Inc
Series
Virtex™ -5r
Type
FPGAr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.HW-V5-PCIE2-UNI-G.pdf
(108 pages)
Specifications of HW-V5-PCIE2-UNI-G
Contents
Board, CD
For Use With/related Products
Virtex™-5 FPGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Table 94: Global Clock Setup and Hold With PLL in System-Synchronous Mode (Cont’d)
DS202 (v5.3) May 5, 2010
Product Specification
Notes:
1.
2.
3.
T
PSPLL
Setup and Hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the
Global Clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the Global
Clock input signal using the fastest process, lowest temperature, and highest voltage. These measurements include PLL CLKOUT0 jitter.
IFF = Input Flip-Flop or Latch.
Use IBIS to determine any duty-cycle distortion incurred using various standards.
Symbol
/ T
PHPLL
No Delay Global Clock and IFF
System-Synchronous Mode
Description
(2)
with PLL in
www.xilinx.com
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
XC5VTX150T
XC5VTX240T
XC5VFX30T
XC5VFX70T
XC5VFX100T
XC5VFX130T
XC5VFX200T
Device
–0.40
–0.30
–0.43
–0.29
1.82
1.79
1.81
1.79
N/A
N/A
N/A
-3
Speed Grade
–0.56
–0.43
–0.40
–0.30
–0.40
–0.28
–0.14
1.82
2.05
1.93
1.90
1.91
1.95
2.06
-2
–0.56
–0.43
–0.40
–0.30
–0.38
–0.24
–0.14
1.95
2.26
2.09
2.07
2.09
2.14
2.29
-1
Units
ns
ns
ns
ns
ns
ns
ns
76