ATF15XX-SAJ44 Atmel, ATF15XX-SAJ44 Datasheet - Page 27

• Manufacturer Part Number: ATF15XX-SAJ44
• Description: ADAPTER FOR ATF15XX-DK2 44PLCC
• Manufacturer: Atmel

Specifications of ATF15XX-SAJ44

• Accessory Type: ATF15xxDK2 Adapter
• For Use With/related Products: 44-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

CPLD Development/Programmer Kit User Guide
The next section of this CPLD design as shown below illustrates how to declare and
assign pin numbers in the CUPL language to the input and output signals. The input and
output pin assignments are assigned according to the connections between the CPLD
and the eight 8-segment LED's as shown in the connection tables (Table 2-1 to Table 2-
8) in Section 2.
Next, the buried signals for the counter and state machine are declared as PINNODE's
as shown below. The feedback and/or the foldback paths available in each macrocell
implement these buried signals. For the listing of the pinnode numbers, please refer to
the "ATF15xx Device Help" section of the ProChip Designer Help File.
After assigning the input, output and buried signals, the related signals (i.e. the LED
segments and buried counter) are grouped together as shown below to make the design
source code more readable and manageable. In CUPL, the "Field" declaration can be
used to group a specific set of signals.
Next, a 21-bit buried up-counter implemented using D-type Flip-flops is shown below
and it is used to divide the 2.0 MHz clock into a 0.954 Hz (2 MHz ÷ 2
nal that can be used to display the text messages. The last bit of this counter is used as
the clock for the state machine that controls the display sequence of the messages on
the LEDs.
/* Inputs */
pin
pin
pin
/* Outputs */
/* DSP1 */
pin
pin
pin
pin
pin
pin
pin
CA0.d = !CA0;
CA1.d = CA0 $ CA1;
CA7.d = (CA6 & CA5 & CA4 & CA3 & CA2 & CA1 & CA0) $ CA7;
CNT_A.ck = MCLK;
CNT_A.ar = !GCLR;
pinnode [618,634,650,687]= [CA20..CA17];
pinnode = [CA16..CA0];
pinnode = [SM7..SM0];
Field DSP1
Field DSP2
Field CNT_A = [CA20..CA0];
Field SM
1
83 = MCLK; /* Global Clock input */
84 = GOE;
49 = LED1A;
46 = LED1B;
48 = LED1C;
50 = LED1D;
52 = LED1E;
51 = LED1F;
54 = LED1G;
:
:
:
= GCLR; /* Global Clear input */
= [LED1G,LED1F,LED1E,LED1D,LED1C,LED1B,LED1A];
= [LED2G,LED2F,LED2E,LED2D,LED2C,LED2B,LED2A];
= [SM7..SM0];
/* GOE1 button used as direction control */
/* LED1 segment A */
/* LED1 segment B */
/* LED1 segment C */
/* LED1 segment D */
/* LED1 segment E */
/* LED1 segment F */
/* LED1 segment G */
CPLD Design Flow Tutorial
21
= 0.954 Hz) sig-
3300A–PLD–08/02
3-7