MA300012 Microchip Technology, MA300012 Datasheet - Page 3

• Manufacturer Part Number: MA300012
• Description: MODULE DSPIC30F SAMPLE 64QFP
• Manufacturer: Microchip Technology

Specifications of MA300012

• Module/board Type: dsPIC30F Plug-in Module
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: DM240001
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Competitive DSP Performance
The dsPIC30F balances its outstanding MCU
qualities with competitive DSP performance.
All the features you require from a high
performance, robust DSP are effortlessly
integrated in the dsPIC DSC.
Best of Both Worlds
Bridging the Performance Gap
Microchip’s dsPIC30F places unprecedented performance in the hands of 16-bit MCU designers. The dsPIC DSC has the
“heart” of a 16-bit MCU with robust peripherals and fast interrupt handling capability and the “brain” of a DSP that manages
high computation activities, creating the optimum single-chip solution for embedded system designs. This enables you to
add powerful new features to your product and integrate functions to save board space.
Outstanding MCU Performance
The first 16-bit MCUs were developed to
overcome the native 64 KB boundary imposed
by 8-bit MCUs. The need for advanced
performance was not contemplated in
these early architectures. When the need
for improved performance became obvious,
next-generation devices were developed, but
were constrained by backward compatibility
requirements and legacy issues.
Developed from the ground up, the dsPIC DSC
addresses traditional 16-bit requirements
without sacrificing performance. It combines
state-of-the-art 16-bit MCU performance in its
general-purpose register-based core with all
the features you need for DSP operations.
•State-centric
•Interrupt intensive
•Cost driven
•Flash capability
•Robust peripherals
•HLL frequently used
MCU Attributes
Advanced interrupt capability
Function
Complex FFT**
Complex FFT**
Complex FFT**
Single Tap FIR
Block FIR
Block FIR Lattice
Block IIR Canonic
Block IIR Lattice
Matrix Add
Matrix Transpose
Vector Dot Product
Vector Max
Vector Multiply
Vector Power
PID Loop Core
*C= #columns, N=# samples, M=#taps, S=#sections, R=#rows
**Complex FFT routine inherently prevents overfl ow
1 cycle = 33 nanoseconds @ 30 MIPS
Flexible re-programmability
Familiar MCU look and feel
Single core architecture
Rich peripheral options
Robust Flash memory
Low pin count options
Robust Data EEPROM
DSP performance
Optimized for C
16+C(6+3(R-1))
46+N(16+7M)
41+N(4+7M)
Cycle Count
36+N(8+7S)
53+N(4+M)
20+3(C*R)
®
19+7(N-2)
Equation
17+3N
17+4N
16+2N
-—
—
—
—
—
N=32, M=32
N=32, M=32
Conditions*
N=32, M=8
N=32, S=4
C=8, R=8
C=8, R=8
N=128
N=256
N=64
N=32
N=32
N=32
N=32
—-
—
Number of
•Flow-centric
•Interrupt averse
•Performance driven
•Emerging Flash
•Limited peripherals
•HLL infrequently used
Cycles
19055
DSP Attributes
3739
8485
1205
7337
1188
2350
212
232
113
229
145
80
1
7
Execution Time
@30 MIPS
124.6 μs
282.8 μs
635.2 μs
244.6 μs
40.2 μs
39.6 μs
78.3 μs
231 ns
7.1 μs
7.7 μs
3.8 μs
7.6 μs
4.8 μs
2.7 μs
33 ns
3