AD5232EVAL50 Analog Devices Inc, AD5232EVAL50 Datasheet - Page 21
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AD5232EVAL50
Manufacturer Part Number
AD5232EVAL50
Description
BOARD EVAL 50 FOR AD5232
Manufacturer
Analog Devices Inc
Datasheet
1.AD5232BRUZ100-RL7.pdf
(24 pages)
Specifications of AD5232EVAL50
Rohs Status
RoHS non-compliant
Table 16 illustrates using the left shift-by-one to change circuit
gain in 6 dB steps.
Table 16.
SDI
0xC1XX
0xC1XX
Table 17 illustrates storing additional data in nonvolatile memory.
Table 17.
SDI
0x3280
0x3340
Table 18 illustrates reading back data from various memory
locations.
Table 18.
SDI
0x94XX
0x00XX
EQUIPMENT CUSTOMER START-UP SEQUENCE
FOR A PCB CALIBRATED UNIT WITH PROTECTED
SETTINGS
1.
2.
3.
FLASH/EEMEM RELIABILITY
The Flash/EE memory array on the AD5232 is fully qualified
for two key Flash/EE memory characteristics: namely, Flash/EE
memory cycling endurance and Flash/EE memory data retention.
Endurance quantifies the ability of the Flash/EE memory to be
cycled through many program, read, and erase cycles. In real
terms, a single endurance cycle is composed of four independent,
sequential events. These events are defined as follows:
1.
2.
3.
4.
For the PCB setting, tie WP to GND to prevent changes in
the PCB wiper set position.
Set power V
As an optional step, strobe the PR pin to ensure full power-
on preset of the wiper register with EEMEM contents in
unpredictable supply sequencing environments.
Initial page erase sequence
Read/verify sequence
Byte program sequence
Second read/verify sequence
SDO
0xXXXX
0xXXXX
SDO
0xXXXX
0xXXXX
0xXXXX
SDO
0xXX80
DD
and V
Action
Moves Wiper W2 to double the present
data value contained in the RDAC2 register
in the direction of Terminal A.
Moves Wiper W2 to double the present
data value contained in the RDAC2 register
in the direction of Terminal A.
Action
Stores 0x80 data in spare EEMEM location,
USER1.
Stores 0x40 data in spare EEMEM location,
USER2.
Action
Prepares data read from USER3 location.
(USER3 is already loaded with 0x80.)
Instruction 0 (NOP) sends 16-bit word out
of SDO where the last eight bits contain
the contents of USER3 location. The NOP
command ensures that the device returns
to the idle power dissipation state.
SS
with respect to GND.
Rev. A | Page 21 of 24
During reliability qualification, Flash/EE memory is cycled
from 0x00 to 0xFF until a first fail is recorded, signifying the
endurance limit of the on-chip Flash/EE memory.
As indicated in the Specifications section, the AD5232 Flash/EE
memory endurance qualification has been carried out in accor-
dance with JEDEC Std. 22, Method A117 over the industrial
temperature range of −40°C to +85°C. The results allow the
specification of a minimum endurance figure over supply and
temperature of 100,000 cycles, with an endurance figure of
700,000 cycles being typical of operation at 25°C.
Retention quantifies the ability of the Flash/EE memory to retain its
programmed data over time. Again, the AD5232 has been qualified
in accordance with the formal JEDEC Retention Lifetime Specifi-
cation (A117) at a specific junction temperature of T
part of this qualification procedure, the Flash/EE memory is cycled
to its specified endurance limit, as described previously, before
data retention is characterized. This means that the Flash/EE
memory is guaranteed to retain its data for its full specified
retention lifetime every time the Flash/EE memory is repro-
grammed. It should also be noted that retention lifetime, based
on an activation energy of 0.6 eV, derates with T
Figure 44.
EVALUATION BOARD
Analog Devices, Inc., offers a user-friendly EVAL-AD5232-10EBZ
evaluation kit that can be controlled by a personal computer
through a printer port. The driving program is self-contained;
no programming languages or skills are needed.
300
250
200
150
100
50
0
40
Figure 44. Flash/EE Memory Data Retention
50
T
J
60
JUNCTION TEMPERATURE (°C)
ADI TYPICAL PERFORMANCE
AT T
J
70
= 55°C
80
90
J
, as shown in
100
J
= 55°C. As
AD5232
110