AD8367-EVAL Analog Devices Inc, AD8367-EVAL Datasheet
AD8367-EVAL
Specifications of AD8367-EVAL
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AD8367-EVAL Summary of contents
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... A single external capacitor sets up the loop averaging time. The AD8367 can be powered on or off by a voltage applied to the ENBL pin. When this voltage logic LO, the total power dissipation drops to the milliwatt range. For a logic HI, the chip powers up rapidly to its normal quiescent current 25° ...
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... AD8367 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Absolute Maximum Ratings............................................................ 5 ESD Caution.................................................................................. 5 Pin Configuration and Function Descriptions............................. 6 Typical Performance Characteristics ............................................. 7 Theory of Operation ...................................................................... 11 Input Attenuator and Gain Control ......................................... 11 Input and Output Interfaces...................................................... 11 Power and Voltage Metrics........................................................ 12 REVISION HISTORY 7/05— ...
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... Pin ENBL Time delay following transition until device meets full specifications. ENBL ENBL Maximum gain Minimum gain Maximum gain MHz MHz 0.5 V GAIN V = 0.5 V GAIN Rev Page AD8367 Min Typ Max Unit LF 500 MHz 45 dB 700 mV p-p 175 200 225 Ω ...
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... AD8367 Parameter f = 140 MHz Gain Gain Scaling Factor Gain Intercept Noise Figure Output IP3 Output 1 dB Compression Point f = 190 MHz Gain Gain Scaling Factor Gain Intercept Noise Figure Output IP3 Output 1 dB Compression Point f = 240 MHz Gain Gain Scaling Factor Gain Intercept ...
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... 200 mV section of this specification is not implied. Exposure to absolute S 1.2 V maximum rating conditions for extended periods may affect ±600 mV device reliability. 250 mW 150°C/W 125°C −40°C to +85°C −65°C to +150°C 300°C Rev Page AD8367 ...
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... Positive Supply Voltage HPFL High-Pass Filter Connection. A capacitor to ground sets the corner frequency of the output offset control loop. ICOM ICOM 1 14 ENBL HPFL 2 13 INPT VPSI 3 12 AD8367 MODE VPSO 4 11 TOP VIEW (Not to Scale) GAIN VOUT 5 10 DETO DECL 6 9 ICOM ...
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... V (V) GAIN Figure 7. NF (re 200 Ω) vs MHz GAIN 40 70MHz 35 30 140MHz 25 240MHz 0.1 0.2 0.3 0.4 0.5 0.6 0.7 V (V) GAIN Figure 8. OIP3 vs. V GAIN AD8367 230 250 ` 0.8 0.9 1.0 10MHz 0.8 0.9 1.0 ...
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... AD8367 100 FREQUENCY (MHz) Figure 9. OIP3 vs. Frequency for –2 –4 –6 –8 0 0.1 0.2 0.3 0.4 0.5 0.6 V (V) GAIN Figure 10. Output P1dB vs –1 –2 –3 –4 –5 10 100 FREQUENCY (MHz) Figure 11. Output P1dB vs. Frequency 1000 = 500 mV GAIN 11 10MHz 70MHz 9 140MHz ...
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... MHz to 500 MHz for Multiple Values of V GAIN V GAIN V OUT TIME (200ns/DIV) Figure 19. AGA Time Domain Response (3 dB Steps) 10nF 1nF 10pF 100pF NO CAP 1 10 100 1k 10k FREQUENCY (kHz) Figure 20. Gain vs. Frequency for Multiple Values of HPFL Capacitor 500 mV GAIN AD8367 30 0 330 100k ...
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... AD8367 1.0 0.9 0.8 140MHz 70MHz 0.7 0.6 0.5 240MHz 0.4 10MHz 0.3 0.2 0.1 0 –60 –50 –40 –30 –20 INPUT LEVEL (dBV rms) Figure 21. AGC RSSI (Voltage on DETO Pin) vs. Input Power at 10 MHz, 70 MHz, 140 MHz, and 240 MHz 1.0 ...
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... The output impedance is determined by an internal 50 Ω damping resistor, as shown in Figure 29. Despite the fact that the output impedance is 50 Ω, the AD8367 should still be presented with a load of 200 Ω. This implies that the load is mismatched, but doing so preserves the distortion performance of the amplifier ...
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... OUTPUT CENTERING To maximize the ac swing at the output of the AD8367, the output level is centered midway between ground and the supply. This is achieved when the DECL pin is bypassed to ground via a shunt capacitor. The loop acts to suppress deviations from the reference at outputs below its corner frequency while not affect- ing signals above it, as shown in Figure 31 ...
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... RMS DETECTION The AD8367 contains a square-law detector that senses the output signal and compares calibrated setpoint of 354 mV rms, which corresponds p-p sine wave. This setpoint is internally set and cannot be modified to change the AGC setpoint and the resulting VOUT level without using additional external components ...
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... Pin DECL to Pin OCOM is recommended to decouple the output reference voltage. INPUT AND OUTPUT MATCHING The AD8367 is designed to operate in a 200 Ω impedance system. The output amplifier is a low output impedance voltage buffer with a 50 Ω damping resistor to desensitize it from load reactance and parasitics. The quoted performance includes the voltage division between the 50 Ω ...
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... OCOM 7 8 Figure 33. Basic Connections for Voltage Controlled Gain Mode MODULATED GAIN MODE The AD8367 can be used as a means of modulating the signal level. Keep in mind, however, that the gain is a nonlinear (exponential) function thus not suitable for GAIN normal amplitude-modulation functions. The small signal bandwidth of the gain interface is ~5 MHz, and the slew rate is of the order of ± ...
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... AD820 (U3) to form the gain control voltage that is applied to the GAIN input of the AD8367 through the divider composed of R4 and R5. This divider is included in order to minimize overload recovery time of the loop by having the integrator saturate at a point that only slightly overdrives the gain control input of the AD8367 ...
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... 10kΩ Note that in this circuit the AD8367’s MODE pin must be pulled high to obtain correct feedback polarity because the integrator inverts the polarity of the feedback signal. The relationship between the setpoint voltage and the rms output voltage of the AD8367 is ...
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... AD8367 –20 –25 –30 –35 –40 380MHz –45 –50 10MHz –55 –60 –20 –15 –10 –5 POUT (dBm INTO 200Ω) Figure 40. ACPR vs. Output Power for QPSK Waveform (QPSK: 4.096 MS/s; α = 0.22; 1 User) Table 6. Suggested Component Values for External AGC Detector Circuit ...
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... EVALUATION BOARD Figure 42 shows the schematic of the AD8367 evaluation board. The board is powered by a single supply of 2 5.5 V. TP3 MODE J1 INPUT R1 57.6Ω GAIN Figure 43. Layout of Component Side R7 SW2 10kΩ LK1 AD8367 ICOM ICOM 1 14 ENBL HPFL 174Ω INPT ...
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... V LK1 Device Enable. When LK1 is installed, the ENBL pin is connected to the positive supply and the AD8367 is in operating mode. R1, R2 Input Interface. R1 and R2 are used to provide an L-pad impedance-transforming network. The broadband matching network transforms a 50 Ω source to match a 200 Ω ...
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... ORDERING GUIDE Model Temperature Range AD8367ARU −40°C to +85°C AD8367ARU-REEL-7 −40°C to +85°C 1 AD8367ARUZ −40°C to +85°C AD8367ARUZ-RL7 1 −40°C to +85°C AD8367-EVAL Pb-free part. 5.10 5.00 4. 6.40 BSC 1 7 0.65 BSC 0.20 1.20 0.09 MAX 0 ...
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... AD8367 NOTES Rev Page ...
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... NOTES Rev Page AD8367 ...
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... AD8367 NOTES © 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C02710–0–7/05(A) Rev Page ...