AD9876-EB Analog Devices Inc, AD9876-EB Datasheet
AD9876-EB
Specifications of AD9876-EB
Related parts for AD9876-EB
AD9876-EB Summary of contents
Page 1
... The AD9876 ADC and/or DAC can also be used at sampling rates as high as 64 MSPS in a 6-bit resolution nonmulti- plexed mode. The AD9876 is pin compatible with the 10-bit AD9875. Both are available in a space-saving 48-lead LQFP package. They are speci- fied over the industrial (–40°C to +85°C) temperature range. ...
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... Output Offset (Single-Ended) Differential Nonlinearity Integral Nonlinearity Output Capacitance Phase Noise @ 1 kHz Offset, 10 MHz Signal Signal-to-Noise and Distortion (SINAD) 10 MHz Analog Out AD9876 (20 MHz BW) Wideband SFDR (to Nyquist, 64 MHz Max) 5 MHz Analog Out 10 MHz Analog Out Narrow-Band SFDR (3 MHz Window): 10 MHz Analog Out IMD ( ...
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... III 25°C III Full II Full II Full II Full II Full II Full II Full II Full II Full II Full II Full II ) Full II RL –3– AD9876 Min Typ Max Unit – ± 0.4 dB ± 1.0 dB ± 10 LSB ± 0 Vppd 4 pF Ω 270 50 MHz µV rms 16 µV rms ...
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... AD9876 Parameter Tx PATH INTERFACE Maximum Input Nibble Rate, 2× Interpolation Tx Setup Time ( Hold Time ( PATH INTERFACE Maximum Output Nibble Rate Rx Data Valid Time ( Data Hold Time ( SERIAL CONTROL BUS Maximum SCLK Frequency (f ) SCLK Clock Pulsewidth High (t ) PWH Clock Pulsewidth Low (t ) PWL ...
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... Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Model Temperature Range AD9876BST –40°C to +85°C AD9876-EB –40°C to +85°C AD9876BSTRL –40°C to +85°C CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection ...
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... ADC Reference Decoupling Node ADC Reference Decoupling Node Receive Path + Input Receive Path – Input Crystal Oscillator Inverter Output PIN CONFIGURATION OSCIN 1 PIN 1 SENABLE 2 IDENTIFIER SCLK 3 SDATA 4 AVDD 5 AD9876 AVSS 6 TOP VIEW Tx+ 7 (Not to Scale) Tx– 8 AVSS 9 FSADJ 10 REFIO 11 PWR –6– 36 DRVSS ...
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... The ADC output codes’ standard deviation is calculated in LSB and converted to an equivalent voltage. This results in a noise figure that can be directly referred to the Rx input of the AD9876. SIGNAL-TO-NOISE AND DISTORTION RATIO (SINAD) SINAD is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc ...
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... AD9876 –Typical Tx Digital Filter Performance Characteristics 10 0 INTERPOLATION –10 FILTER –20 –30 –40 INCLUDING SIN(X)/X –50 –60 –70 –80 –90 –100 0.0 0.1 0.2 0.3 0.4 0.5 0.6 NORMALIZED – TPC 1. 4 Low-Pass Interpolation Filter 10 INTERPOLATION 0 FILTER –10 –20 –30 INCLUDING SIN(X)/X – ...
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... DATA and 50 MSPS 10 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 6.5 7.2 7.3 7.4 7 MSPS, TPC 12. Dual-Tone Spectral Plot @ f DATA f = 6.9 MHz and 7.1 MHz, 2 OUT –9– AD9876 = 100 ) DAC f = 50MSPS DATA f = 32MSPS DATA – MHz ...
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... AD9876 Typical AC Characteristics Curves for TxDAC 10 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 – FREQUENCY OFFSET – kHz TPC 13. Phase Noise Plot @ MHz, 4 LPF OUT 10 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –1 ...
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... MHz, ADC 2.5 2.4 2.3 2.2 2.1 2.0 1.9 1.8 1.7 1.6 1.5 –11– AD9876 112 128 144 160 TPC 19. f vs. Tuning Target MHz, C ADC LPF with Wideband Rx LPF = 0 –6 –4 – VGA GAIN – dB TPC 20. PGA Gain Step Size vs. Gain ...
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... AD9876 Typical AC Characterization Curves for Rx Path LOG MAG 5dB/REF – 0dB 0 1MHz 10MHz TPC 21. Rx LPF Frequency Response, Low f Nominal Tuning Targets LOG MAG 5dB/REF 0dB 1MHz 10MHz TPC 22. Rx LPF Frequency Response, High f Nominal Tuning Targets LOG MAG 5dB/REF 0dB ...
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... ADC 2800 2600 2400 TPC 32. Rx Path Setting, 1/2 Scale Falling Step with Gain Change –13– AD9876 5ns/REF 0s 29.97ns 29.5MHz 0 10MHz 100MHz , 0 60 and C FILTER ENABLED FILTER BYPASSED – GAIN SETTING MSPS MHz ...
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... AD9876 Typical AC Characterization Curves for Rx Path 11.0 10.5 f OSCIN 10.0 9.5 9.0 f PLLB/2 8.5 8.0 7.5 7 – MHz S TPC 33. Rx Path ENOB vs. f ADC 11.0 10.5 f OSCIN 10.0 9.5 9.0 f PLLB/2 8.5 8.0 7.5 7 – MHz IN TPC 36. Rx Path ENOB vs 11.0 10 ...
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... TRANSMIT PATH The AD9876 transmit path consists of a digital interface port, a programmable interpolation filter, and a transmit DAC. All clock signals required by these blocks are generated from the f signal by the PLL-A clock generator. The block diagram OSCIN below shows the interconnection between the major functional components of the transmit path ...
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... AD9876 D/A CONVERTER The AD9876 DAC provides differential output current on the Tx+ and Tx– pins. The value of the output currents are comple- mentary, meaning that they will always sum to I current of the DAC. For example, when the current from Tx full-scale, the current from Tx– is zero. The two currents will typically drive a resistive load that will convert the output currents to a voltage. The Tx+ and Tx– ...
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... The digital HPF introduces a 1 ADC clock cycle latency. If the HPF function is not desired, the HPF can be bypassed and the latency will not be incurred. REV. A CLOCK AND OSCILLATOR CIRCUITRY The AD9876’s internal oscillator generates all sampling clocks A/D from a fundamental frequency quartz crystal. Figure 3a shows GAIN SHA ...
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... Tx [5:0] GAIN Receive Port Timing The AD9876 receives port consists of a six bit databus Rx [5:0], a clock, and an Rx SYNC signal. Two consecutive nibbles of the Rx data are multiplexed together to form a 10-/12-bit data-word. The Rx data is valid on the rising edge of CLK-A when the ADC Clock Source PLL-B/2 Bit (Register 3, Bit 6) is set to 0 ...
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... AD9876 and to run the internal state machines. SCLK maximum frequency is 25 MHz. All data transmitted to the AD9876 is sampled on the rising edge of SCLK. All data read from the AD9876 is validated on the rising edge of SCLK and is updated on the falling edge. SENABLE—Serial Interface Enable The SENABLE pin is active low ...
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... The serial port is operated by an internal state machine and is dependent on the number of SCLK cycles since the last time SENABLE went active. On every eighth rising edge of SCLK, a byte is transferred over the SPI. During a multibyte write cycle, this means the registers of the AD9876 are not simultaneously ...
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... Setting this bit high bypasses the 4-pole LPF. The filter is auto- matically powered down when this bit is set. Bit 1: Enable 1-Pole Rx LPF The AD9876 can be configured with an additional 1-pole ~16 MHz input filter for applications that require steeper filter roll-off or want to use the 1-pole filter instead of the 4-pole receive low- pass filter ...
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... Tx path. This creates a six bit data path. The state of Tx SYNC is ignored in this mode. Bit 2: Transmit Port Least Significant Nibble First Setting Bit 2 high reconfigures the AD9876 for a Transmit Mode that expects least significant nibble before the most significant nibble. ...
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... The power plane is split into a 3VDD section used for the 3 V digital logic circuits, a DVDD section used to supply the digital supply pins of the AD9876, an AVDD section used to supply the analog supply pins of the AD9876/AD9875, and a VANLG section that supplies the higher voltage analog components on the board ...
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... Pins 5, 38, 47, 14, and 35). The decoupling caps should be placed as close to the MxFE supply pins as possible. An example of the proper decoupling is shown in the AD9876 evaluation board schematic. Ground Planes In general, if the component placing guidelines discussed earlier can be implemented best to have at least one continuous ground plane for the entire board ...