EVAL-AD73360LEB Analog Devices Inc, EVAL-AD73360LEB Datasheet
EVAL-AD73360LEB
Specifications of EVAL-AD73360LEB
Related parts for EVAL-AD73360LEB
EVAL-AD73360LEB Summary of contents
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GENERAL DESCRIPTION The AD73360L is a six-input channel analog front-end proces- sor for general-purpose applications, including industrial power VINP1 SIGNAL CONDITIONING VINN1 VINP2 SIGNAL CONDITIONING VINN2 VINP3 SIGNAL CONDITIONING VINN3 REFCAP REFOUT VINP4 SIGNAL CONDITIONING VINN4 VINP5 SIGNAL CONDITIONING ...
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AD73360L–SPECIFICATIONS Parameter REFERENCE REFCAP Absolute Voltage, V REFCAP REFCAP TC REFOUT Typical Output Impedance Absolute Voltage, V REFOUT Minimum Load Resistance Maximum Load Capacitance ADC SPECIFICATIONS 2, 3 Maximum Input Range at VIN Nominal Reference Level at VIN (0 dBm0) ...
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Parameter LOGIC OUTPUT V , Output High Voltage Output Low Voltage OL Three-State Leakage Current POWER SUPPLIES AVDD1, AVDD2 DVDD NOTES 1 Operating temperature range is as follows: –40°C to +85°C. Therefore ...
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AD73360L 100 OUTPUT PIN C L 15pF 100 MCLK SCLK SCLK IS INDIVIDUALLY PROGRAMMABLE IN FREQUENCY (MCLK/4 ...
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ABSOLUTE MAXIMUM RATINGS (T = 25°C unless otherwise noted) A AVDD, DVDD to GND . . . . . . . . . . . . . . . . –0 +4.6 V AGND to DGND . . ...
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AD73360L Pin No. Mnemonic Function 1 VINP2 Analog Input to the Positive Terminal of Input Channel 2. 2 VINN2 Analog Input to the Negative Terminal of Input Channel 2. 3 VINP1 Analog Input to the Positive Terminal of Input Channel ...
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TERMINOLOGY Absolute Gain Absolute gain is a measure of converter gain for a known signal. Absolute gain is measured (differentially) with a 1 kHz sine wave at 0 dBm0 for each ADC. The absolute gain specification is used for gain ...
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AD73360L FUNCTIONAL DESCRIPTION General Description The AD73360L is a six-input channel, 16-bit, analog front end. It comprises six independent encoder channels each featuring signal conditioning, programmable gain amplifier, sigma-delta A/D converter and decimator sections. Each of these sections is described ...
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Figure 7 shows the various stages of filtering that are employed in a typical AD73360L application. In Figure 7a we see the trans- fer function of the external analog antialias filter. Even though single RC pole, its ...
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AD73360L Voltage Reference The AD73360L reference, REFCAP bandgap reference that provides a low noise, temperature-compensated reference to the ADC. A buffered version of the reference is also made available on the REFOUT pin and can be used to ...
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Address (Binary) Name 000 CRA 001 CRB 010 CRC 011 CRD 100 CRE 101 CRF 110 CRG 111 CRH DEVICE ADDRESSS C/D R/W Control Frame Description Bit 15 Control/Data When set high, it signifies a ...
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AD73360L CONTROL REGISTER Bit Name 0 DR0 1 DR1 2 SCD0 3 SCD1 4 MCD0 5 MCD1 6 MCD2 7 CEE CONTROL REGISTER C 7 RES Bit Name 0 GPU 1 Reserved 2 Reserved 3 ...
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CONTROL REGISTER E 7 PUI4 Bit Name CONTROL REGISTER F 7 PUI6 Bit Name CONTROL REGISTER G 7 SEEN Bit Name ...
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AD73360L CONTROL REGISTER H 7 INV Bit Name 0 CH1 1 CH2 2 CH3 3 CH4 4 CH5 5 CH6 6 TME 7 INV REGISTER BIT DESCRIPTIONS Control Register A CRA:0 Data/Program Mode. This bit controls the operating mode of ...
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Control Register F CRF:0–2 Input Gain Selection. These bits select the input gain for ADC5. See Table II. CRF:3 Power Control for ADC5 this bit powers up ADC5. CRF:4–6 Input Gain Selection. These bits select the input ...
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AD73360L Decimation Rate Divider The AD73360L features a programmable decimation rate divider that allows users flexibility in matching the AD73360L’s ADC sample rates to the needs of the DSP software. The maximum sample rate available is DMCLK/256 and the other ...
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Refer to Table VII for details of the settings of CRC. CRD–CRF can be used to control the power status of individual channels allowing ...
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AD73360L SDIFS TFS DT ADSP-21xx SCLK SCLK DSP DR SDO RFS SDOFS SDIFS TFS DT ADSP-21xx SCLK SCLK DSP DR SDO RFS SDOFS The second configuration (shown in Figure 12) has the DSP’s Tx data and Rx data connected to ...
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SE SCLK SDOFS UNDEFINED DATA SDO SDIFS SDI CONTROL WORD SE SCLK SDOFS SDO UNDEFINED DATA SDIFS SDI REGISTER READ INSTRUCTION SE SCLK SDOFS SDO CHANNEL 1 ADC SAMPLE WORD SDIFS SDI CONTROL WORD SE SCLK SDOFS SDO CHANNEL 1 ...
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AD73360L Cascade Operation The AD73360L has been designed to support two devices in a cascade connected to a single serial port (see Figure 17). The SPORT interface protocol has been designed so that device addressing is built into the packet ...
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SE SIGNAL SYNCHRONIZED DSP CONTROL TO MCLK 1/2 74HC74 MCLK CLK RESET SIGNAL SYNCHRONIZED DSP CONTROL TO MCLK TO RESET D Q 1/2 74HC74 MCLK CLK RESET PERFORMANCE As the AD73360L is designed to provide high-performance, ...
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AD73360L Figure 23 shows a comparison of SNR results achieved by vary- ing either the Decimation Rate Setting or the DMCLK Rate Settings. 81 DMCLK = MCLK ...
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Digital Interface As there are a number of variations of sample rate and clock speeds that can be used with the AD73360L in a particular appli- cation important to select the best combination to achieve the desired performance. ...
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AD73360L DSP SPORT Interrupts If SPORT interrupts are enabled important to note that the active signals on the frame sync pins do not necessarily corre- spond with the positions in time of where SPORT interrupts are generated. On ...
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Programming a Single AD73360L for Data Mode Operation This section describes a typical sequence in programming a single AD73360L to operate in normal Data Mode. It details the control (program) words that are sent to the device to con- figure ...
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AD73360L Programming a Single AD73360L for Mixed Mode Operation This section describes a typical sequence in programming a single AD73360L to operate in Mixed Mode. The device is configured in Nonframe Sync Loop-Back (see Figure 11), which allows the DSP’s ...
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Configuring a Cascade of Two AD73360Ls to Operate in Data Mode This section describes a typical sequence of control words that would be sent to a cascade of two AD73360Ls to set them up for operation not intended ...
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AD73360L DSP Tx REG CONTROL WORD 1 1000 1001 0000 0011 STEP 1 DSP Tx REG CONTROL WORD 1 1000 0001 0000 0011 STEP 2 DSP Tx REG CONTROL WORD 2 1000 1010 1110 0001 STEP 3 DSP Tx REG ...
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Configuring a Cascade of Two AD73360Ls to Operate in Mixed Mode This section describes a typical sequence of control words that would be sent to a cascade of two AD73360Ls to configure them for operation in Mixed Mode ...
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AD73360L DSP Tx REG CONTROL WORD 1 1000 1001 0000 0011 STEP 1 DSP Tx REG CONTROL WORD 2 1000 0001 0001 0011 STEP 2 DSP Tx REG CONTROL WORD 2 1000 0001 0001 0011 STEP 3 DSP Tx REG ...
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APPENDIX E HISTOGRAMS OF SNR RESULTS f = 8kHz 1kHz IN SCLK = 8MHz –83 –82 –81 –80 –79 –78 THD – 8kHz 1kHz IN SCLK = 8MHz 76 76.5 77 ...
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AD73360L Topic FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...