EVAL-ADUC814QS Analog Devices Inc, EVAL-ADUC814QS Datasheet - Page 49

• Manufacturer Part Number: EVAL-ADUC814QS
• Description: KIT DEV FOR ADUC814 QUICK START
• Manufacturer: Analog Devices Inc
• Series: QuickStart™ Kitr
• Type: 8052-corer

Specifications of EVAL-ADUC814QS

• Contents: Evaluation Board, Power Supply, Cable, Software and Documentation
• For Use With/related Products: ADuC814
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

TCON
SFR Address
Power-On Default
Bit Addressable
1
Table 23. TCON SFR Bit Designations
Bit No.
7
6
5
4
3
2
1
0
Timer/Counter 0 and 1 Data Registers
Each timer consists of two 8-bit registers. These can be used as independent registers or combined to be a single 16-bit register, depending
on the timer mode configuration.
TH0 and TL0
SFR Address
TH1 and TL1
SFR Address
These bits are not used in the control of Timer/Counter 0 and 1, but are used instead in the control and monitoring of the external INT0 and INT1 interrupt pins.
TF1
Name
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
Timer 0 high byte and low byte.
8CH, 8AH, respectively
Timer 1 high byte and low byte.
8DH, 8BH, respectively
Description
Timer 1 Overflow Flag.
Set by hardware on a Timer/Counter 1 overflow.
Cleared by hardware when the program counter (PC) vectors to the interrupt service routine.
Timer 1 Run Control Bit.
Set by the user to turn on Timer/Counter 1.
Cleared by the user to turn off Timer/Counter 1.
Timer 0 Overflow Flag.
Set by hardware on a Timer/Counter 0 overflow.
Cleared by hardware when the PC vectors to the interrupt service routine.
Timer 0 Run Control Bit.
Set by the user to turn on Timer/Counter 0.
Cleared by the user to turn off Timer/Counter 0.
External Interrupt 1 (INT1) Flag.
Set by hardware by a falling edge or zero level being applied to external interrupt pin INT1 , depending on bit IT1
state.
Cleared by hardware when the when the PC vectors to the interrupt service routine only if the interrupt was
transition-activated. If level-activated, the external requesting source controls the request flag, rather than the on-
chip hardware.
External Interrupt 1 (IE1) Trigger Type.
Set by software to specify edge-sensitive detection, that is, 1-to-0 transition.
Cleared by software to specify level-sensitive detection, that is, zero level.
External Interrupt 0 (INT0) Flag.
Set by hardware by a falling edge or zero level being applied to external interrupt pin INT0, depending on bit IT0
state.
Cleared by hardware when the PC vectors to the interrupt service routine, but only if the interrupt was transition-
activated. If level-activated, the external requesting source controls the request flag, rather than the on-chip
hardware.
External Interrupt 0 (IE0) Trigger Type.
Set by software to specify edge-sensitive detection, that is, 1-to-0 transition.
Cleared by software to specify level-sensitive detection, that is, zero level.
TR1
Timer/Counter 0 and 1 Control Register
88H
00H
Yes
TF0
TR0
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IE1
1
IT1
1
IE0
ADuC814
IT0
1