EVAL-AD1835AEB Analog Devices Inc, EVAL-AD1835AEB Datasheet - Page 21

• Manufacturer Part Number: EVAL-AD1835AEB
• Description: BOARD EVALUATION FOR AD1835A
• Manufacturer: Analog Devices Inc
• Type: ADC + DAC, Codec, Front Endr

Specifications of EVAL-AD1835AEB

• Contents: Evaluation Board
• For Use With/related Products: AD1835A
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

CASCADE MODE
Dual AD1835A Cascade
The AD1835A can be cascaded to an additional AD1835A
which, in addition to six external stereo ADCs, can be used to
create a 32-channel audio system with 16 inputs and 16 outputs.
The cascade is designed to connect to a SHARC DSP and oper-
ates in a time division multiplexing (TDM) format. Figure 16
shows the connection diagram for cascade operation. The digital
interface for both parts must be set to operate in Auxiliary 512
mode by programming ADC Control Register 2. AD1835A No. 1
is set as a master device by connecting the M/S pin to DGND
and AD1835A No. 2 is set as a slave device by connecting the
M/S to ODVDD. Both devices should be run from the same
MCLK and PD/RST signals to ensure that they are synchronized.
REV. A
(SLAVE)
SHARC
ABCLK
TFSx/
DTx
DRx
RFSx
RCLKx
TCLKx
DTx
DRx
RFSx
TFSx
DRx
DTx
L1
L1
AUX ADC
(SLAVE)
L2
MSB
L2
MSB
ASDATA
ALRCLK
ABCLK
AD1835A No. 1 DACs
AD1835A No. 1 ADCs
Figure 17. Dual AD1835A Cascade Timing
L3
L3
MSB – 1
MSB – 1
256 ABCLKs
Figure 16. Dual AD1835A Cascade
AUX ADC
L4
L4
(SLAVE)
R1
R1
32 ABCLKs
R2
R2
AD1835A No. 1
LSB
LSB
(MASTER)
AUX ADC
(SLAVE)
R3
R3
DSDATA
–21–
R4
R4
DON’T CARE
With Device 1 set as a master it will generate the frame-sync and
bit clock signals. These signals are sent to the SHARC and
Device 2, ensuring that both know when to send and receive data.
The cascade can be thought of as two 256 bit shift registers, one for
each device. At the beginning of a sample interval, the shift regis-
ters contain the ADC results from the previous sample interval.
The first shift register (Device 1) clocks data into the SHARC and
clocks in data from the second shift register (Device 2). While this
is happening, the SHARC is sending DAC data to the second shift
register. By the end of the sample interval, all 512 bits of ADC data
in the shift registers will have been clocked into the SHARC and
replaced by DAC data, which is subsequently written to the DACs.
Figure 17 shows the timing diagram for the cascade operation.
L1
L1
L2
L2
AUX ADC
(SLAVE)
AD1835A No. 2 DACs
AD1835A No. 2 ADCs
L3
L3
256 ABCLKs
ASDATA
ALRCLK
ABCLK
L4
L4
R1
R1
AUX ADC
(SLAVE)
R2
R2
R3
R3
AD1835A No. 2
(SLAVE)
AUX ADC
R4
(SLAVE)
R4
DSDATA
AD1835A