AD9460-105LVDS/PCB Analog Devices Inc, AD9460-105LVDS/PCB Datasheet - Page 8

• Manufacturer Part Number: AD9460-105LVDS/PCB
• Description: BOARD EVAL FOR AD9460-105
• Manufacturer: Analog Devices Inc

Specifications of AD9460-105LVDS/PCB

• Number Of Adc's: 1
• Number Of Bits: 16
• Sampling Rate (per Second): 105M
• Data Interface: Parallel
• Inputs Per Adc: 1 Differential
• Input Range: *
• Power (typ) @ Conditions: 1.9W @ 105MSPS
• Voltage Supply Source: Single
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: AD9460-105
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9460
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Table 7. Pin Function Descriptions—100-Lead TQFP_EP in LVDS Mode
Pin No.
1
2
3
4
5
6, 18 to 20, 32 to 34, 36, 38,
43 to 45, 92 to 97
7
8
9, 21, 24, 39, 42, 46, 91, 98,
99, Exposed Heat Sink
DNC = DO NOT CONNECT
OUTPUT MODE
LVDS_BIAS
DCS MODE
AVDD1
SENSE
AVDD2
AVDD2
AVDD2
AVDD2
AVDD2
AVDD2
AVDD1
AVDD1
AVDD1
AVDD2
AGND
AGND
AGND
VREF
REFB
REFT
VIN+
DNC
VIN–
DFS
Mnemonic
DCS MODE
DNC
OUTPUT MODE
DFS
LVDS_BIAS
AVDD1
SENSE
VREF
AGND
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
1
3
9
2
4
5
6
7
8
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
PIN 1
Figure 4. 100-Lead TQFP_EP Pin Configuration in LVDS Mode
Description
Clock Duty Cycle Stabilizer (DCS) Control Pin. CMOS compatible.
Do Not Connect. This pin should float.
CMOS-Compatible Output Logic Mode Control Pin.
Data Format Select Pin. CMOS control pin that determines the format of the output data.
Set Pin for LVDS Output Current. Place a 3.7 kΩ resistor terminated to DRGND.
3.3 V (±5%) Analog Supply.
Reference Mode Selection. Connect to AGND for internal 1.7 V reference (3.4 V p-p analog
input range); connect to AVDD1 for external reference.
1.7 V Reference I/O. The function is dependent on the SENSE pin and external
programming resistors. Decouple to ground with 0.1 μF and 10 μF capacitors.
Analog Ground. The exposed heat sink on the bottom of the package must be connected
to AGND.
DCS = low (AGND) to enable DCS (recommended).
DCS = high (AVDD1) to disable DCS.
OUTPUT MODE = 0 for CMOS mode.
OUTPUT MODE = 1 (AVDD1) for LVDS outputs.
DFS = high (AVDD1) for twos complement
DFS = low (ground) for offset binary format.
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LVDS MODE
(Not to Scale)
AD9460
TOP VIEW
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DRGND
D10+
D10–
D9+
D9–
D8+
D8–
DCO+
DCO–
D7+
D7–
DRVDD
DRGND
D6+
D6–
D5+
D5–
D4+
D4–
D3+
D3–
D2+
D2–
D1+
D1–