AD9246-105EB Analog Devices Inc, AD9246-105EB Datasheet - Page 18

• Manufacturer Part Number: AD9246-105EB
• Description: BOARD EVAL FOR 105MSPS AD9246
• Manufacturer: Analog Devices Inc

Specifications of AD9246-105EB

• Number Of Adc's: 1
• Number Of Bits: 14
• Sampling Rate (per Second): 105M
• Data Interface: Serial
• Inputs Per Adc: 1 Differential
• Input Range: 2 Vpp
• Power (typ) @ Conditions: 373mW @ 105MSPS
• Voltage Supply Source: Single
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: AD9246-105
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

AD9246
If the internal reference of the AD9246 is used to drive multiple
converters to improve gain matching, the loading of the reference
by the other converters must be considered. Figure 44 depicts
how the internal reference voltage is affected by loading.
0.1µF
–0.25
–0.50
–0.75
–1.00
–1.25
0.1µF
0
0
Figure 43. Programmable Reference Configuration
0.1µF
Figure 42. Internal Reference Configuration
0.1µF
VREF
SENSE
VREF
VIN+
VIN–
Figure 44. VREF Accuracy vs. Load
SENSE
0.5
R2
R1
VIN+
VIN–
LOAD CURRENT (mA)
SELECT
LOGIC
VREF = 1V
SELECT
1.0
LOGIC
CORE
ADC
AD9246
CORE
0.5V
ADC
AD9246
0.5V
VREF = 0.5V
1.5
REFT
REFB
0.1µF
REFT
REFB
0.1µF
2.0
Rev. A | Page 18 of 44
External Reference Operation
The use of an external reference may be necessary to enhance
the gain accuracy of the ADC or improve thermal drift charac-
teristics. Figure 45 shows the typical drift characteristics of the
internal reference in both 1 V and 0.5 V modes.
When the SENSE pin is tied to AVDD, the internal reference is
disabled, allowing the use of an external reference. An internal
resistor divider loads the external reference with an equivalent
6 kΩ load (see Figure 11). In addition, an internal buffer
generates the positive and negative full-scale references for the
ADC core. Therefore, the external reference must be limited to
a maximum of 1 V.
CLOCK INPUT CONSIDERATIONS
For optimum performance, the AD9246 sample clock inputs
(CLK+ and CLK−) should be clocked with a differential signal.
The signal is typically ac-coupled into the CLK+ pin and the
CLK− pin via a transformer or capacitors. These pins are biased
internally (see Figure 5) and require no external bias.
Clock Input Options
The AD9246 has a very flexible clock input structure. The clock
input can be a CMOS, LVDS, LVPECL, or sine wave signal.
Regardless of the type of signal used, the jitter of the clock
source is of the most concern (see the Jitter Considerations
section).
Figure 46 shows one preferred method for clocking the
AD9246. A low jitter clock source is converted from single-
ended to a differential signal using an RF transformer. The
back-to-back Schottky diodes across the transformer secondary
limit clock excursions into the AD9246 to approximately
0.8 V p-p differential. This helps prevent the large voltage
swings of the clock from feeding through to other portions of
the AD9246, while preserving the fast rise and fall times of the
signal, which are critical to a low jitter performance.
10
0
8
6
4
2
–40
–20
VREF = 0.5V
Figure 45. Typical VREF Drift
0
TEMPERATURE (°C)
VREF = 1V
20
40
60
80