AD9786-EB Analog Devices Inc, AD9786-EB Datasheet - Page 20

• Manufacturer Part Number: AD9786-EB
• Description: BOARD EVALUATION FOR AD9786
• Manufacturer: Analog Devices Inc
• Series: TxDAC+®r

Specifications of AD9786-EB

• Number Of Dac's: 1
• Number Of Bits: 16
• Outputs And Type: 1, Differential
• Sampling Rate (per Second): 500M
• Data Interface: Parallel
• Dac Type: Current
• Voltage Supply Source: Single
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: AD9786
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

AD9786
SERIAL CONTROL INTERFACE
The AD9786 serial port is a flexible, synchronous serial commu-
nications port, allowing easy interface to many industry-standard
microcontrollers and microprocessors. The serial I/O is compatible
with most synchronous transfer formats, including both the
Motorola SPI® and Intel® SSR protocols. The interface allows
read/write access to all registers that configure the AD9786. Single-
or multiple-byte transfers are supported, as well as MSB-first or
LSB-first transfer formats. The AD9786 serial interface port can
be configured as a single pin I/O (SDIO), or as two unidirectional
pins for input/output (SDIO/SDO).
GENERAL OPERATION OF THE SERIAL INTERFACE
There are two phases to a communication cycle with the AD9786.
Phase 1 is the instruction cycle, which is the writing of an
instruction byte into the AD9786, coincident with the first eight
SCLK rising edges. The instruction byte provides the AD9786
serial port controller with information regarding the data transfer
cycle, which is Phase 2 of the communication cycle. The Phase 1
instruction byte defines whether the upcoming data transfer is a
read or a write, the number of bytes in the data transfer, and the
starting register address for the first byte of the data transfer. The
first eight SCLK rising edges of each communication cycle are
used to write the instruction byte into the AD9786.
A logic high on the CSB pin, followed by a logic low, resets the
SPI port timing to the initial state of the instruction cycle. This
is true regardless of the present state of the internal registers or
the other signal levels present at the inputs to the SPI port. If the
SPI port is in the midst of an instruction cycle or a data transfer
cycle, none of the present data is written.
The remaining SCLK edges are for Phase 2 of the communication
cycle. Phase 2 is the actual data transfer between the AD9786
and the system controller. Phase 2 of the communication cycle
is a transfer of 1, 2, 3, or 4 data bytes, as determined by the instruc-
tion byte. Using one multibyte transfer is the preferred method.
Single-byte data transfers are useful to reduce CPU overhead
when register access requires one byte only. Registers change
immediately upon writing to the last bit of each transfer byte.
SCLK (PIN 56)
SDIO (PIN 55)
SDO (PIN 54)
CSB (PIN 57)
Figure 36. AD9786 SPI Port Interface
AD9786 SPI
PORT INTERFACE
Rev. B | Page 20 of 56
Instruction Byte
R/ W , Bit 7 of the instruction byte, determines whether a read or
a write data transfer occurs after the instruction byte write.
Logic high indicates a read operation; Logic 0 indicates a write
operation. N1 and N0, Bit 6 and Bit 5 of the instruction byte,
determine the number of bytes to be transferred during the data
transfer cycle (see Table 10).
Table 10. Bytes Transferred During Data Transfer Cycle
N1
0
0
1
1
The bit decodes are shown as follows:
MSB
I7
R/W
A4, A3, A2, A1, and A0 (Bit 4, Bit 3, Bit 2, Bit 1, and Bit 0) of
the instruction byte determine which register is accessed during
the data transfer portion of the communication cycle. For multibyte
transfers, this address is the starting byte address. The remaining
register addresses are generated by the AD9786.
SERIAL INTERFACE PORT PIN DESCRIPTIONS
SCLK—Serial Clock. The serial clock pin is used to
synchronize data to and from the AD9786 and to run the
internal state machines. The maximum frequency of SCLK
is 20 MHz. All data input to the AD9786 is registered on the
rising edge of SCLK. All data is driven out of the AD9786
on the falling edge of SCLK.
CSB—Chip Select. Active low input starts and gates a communi-
cation cycle. It allows more than one device to be used on the
same serial communication lines. The SDO and SDIO pins go
to a high impedance state when this input is high. Chip select
should stay low during the entire communication cycle.
SDIO—Serial Data I/O. Data is always written into the
AD9786 on this pin. However, this pin can be used as a
bidirectional data line. The configuration of this pin is
controlled by Bit 7 of Register Address 0x00. The default is
Logic 0, which configures the SDIO pin as unidirectional.
SDO—Serial Data Out. Data is read from this pin for protocols
that use separate lines for transmitting and receiving data. In
the case where the AD9786 operates in a single bidirectional
I/O mode, this pin does not output data and is set to a high
impedance state.
I6
N1
0
1
0
1
N2
I5
N0
Description
Transfer 1 byte
Transfer 2 bytes
Transfer 3 bytes
Transfer 4 bytes
I4
A4
I3
A3
I2
A2
I1
A1
LSB
I0
A0