ADV212-ASD-P160-EB Analog Devices Inc, ADV212-ASD-P160-EB Datasheet - Page 30

• Manufacturer Part Number: ADV212-ASD-P160-EB
• Description: BOARD EVAL FOR ADV212 CODEC
• Manufacturer: Analog Devices Inc

Specifications of ADV212-ASD-P160-EB

• Module/board Type: Evaluation Board
• For Use With/related Products: ADV212
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

ADV212
PLL REGISTERS
The ADV212 uses the PLL_HI and PLL_LO direct registers to
configure the PLL. Any time the PLL_LO register is modified,
the host must wait at least 20 µs before reading from or writing
to another register. If this delay is not implemented, erratic
behavior may result.
MCLK is the input clock to the ADV212 PLL and is used to
generate the internal JCLK (JPEG2000 processor clock) and
HCLK (embedded CPU clock).
The PLL can be programmed to have any possible final
multiplier value as long as
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Table 20. Recommended PLL Register Settings
IPD
0
0
0
0
1
1
1
1
Table 21. Recommended Values for PLL_HI and PLL_LO Registers
Video Standard
SMPTE 125M or ITU-R BT.656 (NTSC or PAL)
SMPTE 293M (525p)
ITU-R BT.1358 (625p)
SMPTE 274M (1080i)
JCLK > 50 MHz and < 150 MHz (144-pin version).
JCLK > 50 MHz and < 115 MHz (121-pin version).
HCLK < 81 MHz (121-pin version) or HCLK < 108 MHz
(144-pin version).
JCLK ≥ 2 × VCLK for single-component input.
JCLK ≥ 2 × VCLK for YCbCr [4:2:2] input.
In JDATA mode (JDATA), JCLK must be 4 × MCLK
or higher.
The maximum burst frequency for external DMA modes is
≤ 0.36 JCLK.
LFB
0
0
1
1
0
0
1
1
PLLMULT
N
N
N
N
N
N
N
N
HCLKD
0
1
0
1
0
1
0
1
Rev. B | Page 30 of 44
CLKIN Frequency on MCLK
27 MHz
27 MHz
27 MHz
74.25 MHz
HCLK
N × MCLK
N × MCLK/2
2 × N × MCLK
N × MCLK
N × MCLK/2
N × MCLK/4
N × MCLK
N × MCLK/2
MCLK
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To achieve the lowest power consumption, an MCLK frequency
of 27 MHz is recommended for a standard definition CCIR 656
input. The PLL circuit is recommended to have a multiplier of
3. This sets JCLK and HCLK to 81 MHz.
For MCLK frequencies greater than 50 MHz, the input
clock divider must be enabled; that is, IPD must be set
to 1. IPD cannot be enabled for MCLK frequencies
below 20 MHz.
Deinterlace modes require JCLK ≥ 4 × MCLK.
It is not recommended to use an LLC output from a video
decoder as a clock source for MCLK.
IPD
÷2
Figure 32. PLL Architecture and Control Functions
DETECT
LFB
PHASE
÷2
BYPASS
÷PLLMULT
LPF
JCLK
N × MCLK
N × MCLK
2 × N × MCLK
2 × N × MCLK
N × MCLK/2
N × MCLK/2
N × MCLK
N × MCLK
VCO
PLL_HI
0x0008
0x0008
0x0008
0x0008
÷2
÷2
HCLKD
PLL_LO
0x0004
0x0004
0x0004
0x0084
÷2
JCLK
HCLK