ST7MDT20-EVC/US STMicroelectronics, ST7MDT20-EVC/US Datasheet - Page 29

• Manufacturer Part Number: ST7MDT20-EVC/US
• Description: BOARD EVALUATION/TRAINING/PROGRM
• Manufacturer: STMicroelectronics

Specifications of ST7MDT20-EVC/US

• Module/board Type: Evaluation Board
• For Use With/related Products: ST72124,7231x,72321,72334,72511,72512,72521
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 497-2897

.TBIC1LR DS.B
.TBOC1HR DS.B
.TBOC1LR DS.B
.TBCHR DS.B
.TBCLR DS.B
.TBACHR DS.B
.TBACLR DS.B
.TBIC2HR DS.B
.TBIC2LR DS.B
.TBOC2HR DS.B
.TBOC2LR DS.B
;**********************************************************************
;
;**********************************************************************
.SCISR DS.B
.SCIDR DS.B
.SCIBRR DS.B
.SCICR1 DS.B
.SCICR2 DS.B
.SCIERPR DS.B 1
.SCIETPR DS.B 1
reserved5 DS.B 24
;**********************************************************************
;
;**********************************************************************
.ADCDR DS.B
.ADCCSR DS.B
;**********************************************************************
;**********************************************************************
WORDS
;**********************************************************************
; for ST72334J2 or ST72334N2 with 8K ROM & 384 bytes RAM
;**********************************************************************
;**********************************************************************
;**********************************************************************
;**********************************************************************
; for ST72334J4 or ST72334N4 with 16K ROM & 512 bytes RAM
;
#ifdef ST72334N2
#endif
#ifdef ST72334N4
segment byte at 80-FF 'ram0' ;Zero Page
segment byte at 100-1FF
segment byte at E000-FFDF 'rom' ;
segment byte at C00-CFF 'eeprom' ;EEPROM area
segment byte at 100-1FF
segment byte at 200-27F
DS.B 1
; following addresses are 16 bit length
SCI registers
ADC registers
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
; reserved
; adc data register
; timer B counter high register
; timer B counter low register
; sci status register
; sci data register
; adc control status register
; timer B alternate counter high register
; timer B alternate counter low register
; sci baud rate register
; sci control register 1
; sci control register 2
; timer B input capture 1 low register
; timer B output compare 1 high register
; timer B output compare 1 low register
; timer B input capture 2 high register
; timer B input capture 2 low register
; timer B output compare 2 high register
; timer B output compare 2 low register
; sci extended receive prescaler register
; sci extended transmit prescaler register
; unused
'stack'
'stack'
'ram1'
APPENDIX 1: ST72334 Register and Memory Mapping File
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