CLC952PCASM National Semiconductor, CLC952PCASM Datasheet - Page 7

• Manufacturer Part Number: CLC952PCASM
• Description: IC CLC952 EVALUATION BOARD
• Manufacturer: National Semiconductor

Specifications of CLC952PCASM

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *CLC952PCASM

AGND
AV
AV
ENCODE
AIN
V
V
DV
DGND
D0-D11
OFFSET
REF
CC
EE
CC
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ENCODE
V
OFFSET
AGND
AGND
AGND
AV
AV
AV
AV
AV
AV
AV
V
AIN
REF
CC
CC
CC
EE
EE
EE
EE
(Pins 1, 6, 13) Analog circuit ground.
(Pins 2, 12, 14) +5V power supply for the analog section. Bypass to analog ground with a 0.1 F capacitor.
(Pins 3, 5, 7,11) -5V power supply for the analog section. Bypass to analog ground with a 0.1 F capacitor.
(Pin 4) ENCODE initiates a new data conversion cycle on each rising edge. Logic for this input is
standard TTL. 50% duty cycle is recommended for full compliance with the guaranteed specifications.
(Pin 8) Ground-centered, DC-coupled analog input with a 1V
+0.5V. Analog input impedance is approximately 500 .
(Pin 9) Voltage offset control. Sets the midpoint of the analog input range. Normally left floating. Ratio
of applied voltage to effective offset is 200:1. (1V applied to V
(Pin 10) Internal voltage reference. Nominally +2.4V. V
source to program gain and input range. Bypass V
(Pin 15) +5V power supply for the digital section. Bypass to digital ground with a 0.1 F capacitor.
(Pin 16) Digital ground.
(Pins 17-28) Digital data outputs are CMOS and TTL compatible. D0 is the LSB and D11
MSB is inverted. Output coding is two’s complement.
10
11
12
13
14
1
2
3
4
5
6
7
8
9
CLC952
28
27
26
25
24
23
22
21
20
19
18
17
16
15
CLC952 Pin Definitions
D11 (MSB INV)
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
DGND
DV
CC
(LSB)
7
REF
REF
to ground with a 0.1 F capacitor.
can be pulled up or down with a voltage
pp
OFFSET
maximum input range from -0.5V to
produces 5mV midpoint offset.)
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is the MSB.