LVDSEVAL-001 National Semiconductor, LVDSEVAL-001 Datasheet - Page 5

• Manufacturer Part Number: LVDSEVAL-001
• Description: EVALUATION BOARD FOR DS90LV031A
• Manufacturer: National Semiconductor

Specifications of LVDSEVAL-001

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *LVDSEVAL-001

LVDS Channel # 3: LVDS Line Driver
This test channel provides test points for an isolated driver with a standard 100 Ohm differential termination
load. Probe access for the driver outputs is provided at test points A3 and B3. The driver input signal (I3) is
terminated with a 50 Ohm termination resistor on the bottom side of the PCB.
LVDS Channel # 4: PCB Interconnect
This test channel connects Driver #4 to Receiver #2 via a pure PCB interconnect. A SMB test point interface
of the LVDS signaling is provided at test points A4 and B4. The driver input signal (I4) is terminated with a
50 Ohm termination resistor on the bottom side of the PCB. The receiver output signal may be probed at
test point O4. A PCB option for a series 450 Ohm resistor is also provided in case 50 Ohm probes are
employed on the receiver output signal. A direct probe connection is possible with a high impedance
probe (>100 k Ohm loading) on the LVDS signals at test points A4 and B4. This channel may be used for
analyzing the LVDS signal without the bandwidth limiting effects of a cable interconnect.
LVDS Channel # 5: LVDS Receiver
This test channel provides test points for an isolated receiver. Termination options on the receiver inputs
accommodate either a 100 Ohm resistor connected across the inputs (differential) or two separate 50
Ohm terminations (each line to ground). The second option allows for a standard signal generator inter-
face. Input signals are connected at test points A5 and B5. A PCB option for a series 450 Ohm resistor
is also provided in case 50 Ohm probes are employed on the receiver output signal. The receiver output
signal may be probed at test point O5.
6.1.3 Interconnecting Cable and Connector
The evaluation PCB has been designed to directly accommodate a 25 pair (50-pin) SCSI-2 cable commonly
referred to as an “A” cable. The pinout, connector, and cable electrical/mechanical characteristics are
defined in the SCSI-2 standard and the cable is widely available. The connector is 50 position, with 0.050
centers and the pairs are pinned out up and down. For example pair 1 is on pins 1 and 26, not pins 1 and 2.
IMPORTANT NOTE: The 23 unused pairs and the overall shield are connected to ground. Other cables
may also be used if they are built up.
6.1.4 PCB Design
Due to the high speed switching rates obtainable by LVDS a minimum of a four layer PCB construction
and FR-4 material is recommended. This allows for 2 signal layers and full power and ground planes.
The stack is: signal (LVDS), ground, power, signal (TTL/CMOS).
Differential traces are highly recommended for the driver outputs and the receiver inputs signal (LVDS
signals, see PCB layout between U1 and J3). Employing differential traces will ensure a low emission
design and maximum common mode rejection of any coupled noise. Differential traces require that the
spacing between the differential pair be controlled. This distance should be held as small as possible to
ensure that any noise coupled onto the lines will primarily be common mode. Also by keeping the pair
close together the maximum canceling of fields is obtained. Differential impedance of the trace pair
should be matched to the selected interconnect media (cable’s differential characteristic impedance).
Equations for calculating differential impedance are contained in chapter 4 of the LVDS Owner’s Manual
and also in National application note AN-905 for both microstrip and stripline differential PCB traces.
Termination of LVDS lines is required to complete the current loop and for the drivers to properly oper-
ate. This termination in its simplest form is a single surface mount resistor (surface mount resistor mini-
mizes parasitic elements) connected across the differential pair as close to the receiver inputs as possible
(should be within 0.5 inch (13 mm) of input pins). Its value should be selected to match the intercon-
nects differential characteristics impedance. The closer the match the higher the signal fidelity and the
less common mode reflections will occur (lower emissions too). Typical values are 100 or 121 Ohm ±5%
(media specific).
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