C8051F310DK-H Silicon Laboratories Inc, C8051F310DK-H Datasheet - Page 7

• Manufacturer Part Number: C8051F310DK-H
• Description: DEV KIT FOR C8051F310/F311
• Manufacturer: Silicon Laboratories Inc

Specifications of C8051F310DK-H

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

6.3. Expansion I/O Connector (J1)
The 34-pin Expansion I/O connector J1 provides access to all signal pins of the C8051F310 device. Pins for +3 V,
digital ground and the output of an on-board low-pass filter are also available. A small through-hole prototyping area
is also provided. All I/O signals routed to connector J1 are also routed to through-hole connection points between J1
and the prototyping area (see Figure 2 on page 5). Each connection point is labeled indicating the signal available at
the connection point. See Table 2 for a list of pin descriptions for J1.
6.4. Target Board DEBUG Interface (J4)
The DEBUG connector (J4) provides access to the DEBUG (C2) pins of the C8051F310. It is used to connect the
Serial Adapter or the USB Debug Adapter to the target board for in-circuit debugging and Flash programming.
Table 3 shows the DEBUG pin definitions.
Pin #
10
12
11
1
2
3
4
5
6
7
8
9
+3 VD (+3.3 VDC)
Description
PWM Output
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
P1.0
P1.1
Table 3. DEBUG Connector Pin Descriptions
2, 3, 9
Pin #
10
1
4
5
6
7
8
Table 2. J1 Pin Descriptions
Pin #
13
14
15
16
17
18
19
20
21
22
23
24
+3 VD (+3.3 VDC)
Rev. 0.6
Description
Not Connected
GND (Ground)
Description
/RST (Reset)
USB Power
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
C2CK
C2D
P3.0
Pin #
25
26
27
28
29
30
31
32
33
34
C8051F31x-DK
GND (Ground)
GND (Ground)
Description
/RST (Reset)
P2.6
P2.7
P3.0
P3.1
P3.2
P3.3
P3.4
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