C8051F124-TB Silicon Laboratories Inc, C8051F124-TB Datasheet - Page 60

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C8051F124-TB

Manufacturer Part Number
C8051F124-TB
Description
BOARD PROTOTYPING W/C8051F124
Manufacturer
Silicon Laboratories Inc
Datasheets

Specifications of C8051F124-TB

Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
60
Bits7–4: UNUSED. Read = 0000b; Write = don’t care.
Bit3:
Bit2:
Bit1:
Bit0:
SFR Page:
SFR Address:
Note:
R/W
Bit7
-
AIN67IC: AIN0.6, AIN0.7 Input Pair Configuration Bit.
0: AIN0.6 and AIN0.7 are independent single-ended inputs.
1: AIN0.6, AIN0.7 are (respectively) +, – differential input pair.
AIN45IC: AIN0.4, AIN0.5 Input Pair Configuration Bit.
0: AIN0.4 and AIN0.5 are independent single-ended inputs.
1: AIN0.4, AIN0.5 are (respectively) +, – differential input pair.
AIN23IC: AIN0.2, AIN0.3 Input Pair Configuration Bit.
0: AIN0.2 and AIN0.3 are independent single-ended inputs.
1: AIN0.2, AIN0.3 are (respectively) +, – differential input pair.
AIN01IC: AIN0.0, AIN0.1 Input Pair Configuration Bit.
0: AIN0.0 and AIN0.1 are independent single-ended inputs.
1: AIN0.0, AIN0.1 are (respectively) +, – differential input pair.
The ADC0 Data Word is in 2’s complement format for channels configured as differential.
0
0xBA
R/W
Bit6
-
SFR Definition 5.1. AMX0CF: AMUX0 Configuration
R/W
Bit5
-
R/W
Bit4
-
Rev. 1.4
AIN67IC
R/W
Bit3
AIN45IC
R/W
Bit2
AIN23IC
R/W
Bit1
AIN01IC 00000000
R/W
Bit0
Reset Value

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