C8051F000-TB Silicon Laboratories Inc, C8051F000-TB Datasheet - Page 141
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C8051F000-TB
Manufacturer Part Number
C8051F000-TB
Description
BOARD PROTOTYPING W/C8051F000
Manufacturer
Silicon Laboratories Inc
Specifications of C8051F000-TB
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
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19.1.4. Mode 3: Two 8-bit Counter/Timers (Timer 0 Only)
Timer 0 and Timer 1 behave differently in Mode 3. Timer 0 is configured as two separate 8-bit counter/timers held
in TL0 and TH0. The counter/timer in TL0 is controlled using the Timer 0 control/status bits in TCON and TMOD:
TR0, C/T0, GATE0 and TF0. It can use either the system clock or an external input signal as its timebase. The
TH0 register is restricted to a timer function sourced by the system clock. TH0 is enabled using the Timer 1 run
control bit TR1. TH0 sets the Timer 1 overflow flag TF1 on overflow and thus controls the Timer 1 interrupt.
Timer 1 is inactive in Mode 3, so with Timer 0 in Mode 3, Timer 1 can be turned off and on by switching it into and
out of its Mode 3. When Timer 0 is in Mode 3, Timer 1 can be operated in Modes 0, 1 or 2, but cannot be clocked
by external signals nor set the TF1 flag and generate an interrupt. However, the Timer 1 overflow can be used for
baud rate generation. Refer to Section 18 (UART) for information on configuring Timer 1 for baud rate generation.
141
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
SYSCLK
/INT0
T0
GATE0
Crossbar
Crossbar
12
TR0
TR1
0
1
Figure 19.3. T0 Mode 3 Block Diagram
CKCON
M
T
2
M
T
1
M
T
0
0
1
C/T0
G
A
T
E
1
Rev. 1.7
C
T
1
/
M
T
1
1
TMOD
M
T
1
0
G
A
T
E
0
C
T
0
/
M
T
0
1
M
T
0
0
(8 bits)
(8 bits)
TH0
TL0
TR1
TR0
TF1
TF0
IE1
IT1
IE0
IT0
Interrupt
Interrupt
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