EVAL-ADM1026EB ON Semiconductor, EVAL-ADM1026EB Datasheet - Page 26

• Manufacturer Part Number: EVAL-ADM1026EB
• Description: BOARD EVAL FOR ADM1026
• Manufacturer: ON Semiconductor
• Type: Temperature Sensorr

Specifications of EVAL-ADM1026EB

• Contents: Evaluation Board
• For Use With/related Products: ADM1026
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

pins or fan speed inputs (Pins 3 to 6, and 9 to 12), and one
pin that can be configured as GPIO16 or the bidirectional
THERM pin (Pin 42). The GPIO/FAN pins are configured
as general−purpose logic pins by setting Bits 0 to 7 of
Configuration Register 2 (Address 01h). Pin 42 is
configured as GPIO16 by setting Bit 0 of Configuration
Register 3, or as the THERM function by clearing this bit.
bits in one of the GPIO configuration registers (Addresses
08h to 0Bh), one in the GPIO status registers (Addresses 24h
and 25h), and one in the GPIO mask registers (Addresses
1Ch and 1Dh)
registers makes the corresponding GPIO pin an output.
Clearing the direction bit to 0 makes it an input.
registers makes the corresponding GPIO pin active high.
Clearing the polarity bit to 0 makes it active low.
corresponding bit in one of the GPIO status registers is
read−only, and is set when the input is asserted (“asserted” may
be high or low depending on the setting of the polarity bit).
corresponding bit in one of the GPIO status registers
becomes read/write. Setting this bit then asserts the GPIO
output. (Here again, “asserted” may be high or low
depending on the setting of the polarity bit.)
can be masked out by setting the corresponding bit in one of
the GPIO mask registers. When the pin is configured as an
output, this bit is automatically masked to prevent the data
written to the status bit from causing an interrupt, with the
exception of GPIO16, which must be masked manually by
setting Bit 7 of Mask Register 4 (Reg 1Bh).
connected to external interrupt sources such as temperature
sensors with digital output. Another application of the GPIO
pins would be to monitor a processor’s voltage ID code (VID
code).
ADM1026 Interrupt Structure
Figure 52. Interrupts can come from a number of sources,
Each GPIO pin has four data bits associated with it, two
Setting a direction bit = 1 in one of the GPIO configuration
Setting a polarity bit = 1 in one of the GPIO configuration
When a GPIO pin is configured as an input, the
When a GPIO pin is configured as an output, the
The effect of a GPIO status register bit on the INT output
When configured as inputs, the GPIO pins may be
The Interrupt Structure of the ADM1026 is shown in
START OF ANALOG
MONITORING
CYCLE
INT
OUT-OF-LIMIT
MEASUREMENT
INT CLEARED
Figure 49. Delay After Clearing INT Before Reassertion
LOCAL
TEMPERATURE
MEASUREMENT
http://onsemi.com
START OF ANALOG
MONITORING
CYCLE
26
FULL MONITORING CYCLE = 273ms
which are combined to form a common INT output. When
INT is asserted, this output pulls low. The INT pin has an
internal, 100 kW pullup resistor.
Analog/Temperature Inputs
in the appropriate value register, the value and the limits
from the corresponding limit registers are fed to the high and
low limit comparators. The device performs greater than
comparisons to the high limits. An out−of−limit is also
generated if a result is less than or equal to a low limit. The
result of each comparison (1 = out of limit, 0 = in limit) is
routed to the corresponding bit input of Interrupt Status
Register 1, 2, or 4 via a data de−multiplexer, and used to set
that bit high or low as appropriate. Status bits are
self−clearing. If a bit in a status register is set due to an
out−of−limit measurement, it continues to cause INT to be
asserted as long as it remains set, as described later.
However, if a subsequent measurement is in limit, it is reset
and does not cause INT to be reasserted. Status bits are
unaffected by clearing the interrupt.
corresponding to each of the interrupt status register bits.
Setting an interrupt mask bit high conceals an asserted status
bit from display on Interrupt Pin 17. Setting an interrupt
mask bit low allows the corresponding status bit to be
asserted and displayed on Pin 17. After mask gating, the
status bits are all OR’ed together to produce the analog and
fan interrupt that is used to set a latch. The output of this latch
is OR’ed with other interrupt sources to produce the INT
output. This pulls low if any unmasked status bit goes high,
that is, when any measured value goes out of limit.
temperature measurement is cleared by one of the methods
described later, the latch is reset. It is not set again, and INT
is not reasserted until after two local temperature
measurements have been taken, even if the status bit remains
set or a new analog/temperature event occurs, as shown in
Figure 49. This delay corresponds to almost two monitoring
cycles, and is about 530 ms. However, interrupts from other
sources such as a fan or GPIO can still occur. This is
illustrated in Figure 50.
As each analog measurement value is obtained and stored
Interrupt Mask Registers 1, 2, and 4 have bits
When an INT output caused by an out−of−limit analog/
OUT-OF-LIMIT
MEASUREMENT
MEASUREMENT
TEMPERATURE
LOCAL
INT RE−ASSERTED
START OF ANALOG
MONITORING
CYCLE