EVAL-ADT7462EBZ ON Semiconductor, EVAL-ADT7462EBZ Datasheet - Page 6

• Manufacturer Part Number: EVAL-ADT7462EBZ
• Description: BOARD EVALUATION FOR ADT7462
• Manufacturer: ON Semiconductor
• Type: Temperature Sensorr

Specifications of EVAL-ADT7462EBZ

• Contents: Evaluation Board
• For Use With/related Products: ADT7462
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1. All voltages are measured with respect to GND, unless otherwise specified. Typical values are at T
2. Unused digital inputs connected to GND.
3. Guaranteed by design, not production tested.
4. Note that this specification does not apply if Pin 26 (V
5. For Pin 23 and Pin 24 configured as +1.8V or +2.5V only, restricted conditions of V
ELECTRICAL CHARACTERISTICS
OPEN−DRAIN SERIAL BUS OUTPUT (SDA)
SERIAL BUS DIGITAL INPUTS (SDA AND SCL)
DIGITAL INPUT LOGIC LEVELS (VID0 to VID6) AND THERM, TACH, GPIO, VR_HOT, SCSI_TERM)
DIGITAL INPUT CURRENTS
SERIAL BUS TIMING (Note 3)
Output Low Voltage, V
High Level Output Leakage Current, I
Input High Voltage, V
Input Low Voltage, V
Hysteresis
Input High Voltage, V
Input Low Voltage, V
Input High Voltage, V
Input High Voltage, V
Input Low Voltage, V
Hysteresis
Input High Current, I
Input Low Current, I
Input Capacitance (Note 3)
Clock Frequency
Glitch Immunity, t
Bus Free Time
Start Setup Time, t
Start Hold Time, t
SCL Low Time, t
SCL High Time, t
SCL, SDA Rise Time, t
SCL, SDA Fall Time, t
Data Setup Time, t
Detect Clock Low Timeout
parametric norm. Logic inputs accept input high voltages up to 5.0 V, even when the device is operating at supply voltages below 5.0 V. Timing
specifications are tested at logic levels of V
Performance Characteristics section for V
Parameter
SDA
SCL
LOW
HIGH
SW
HD;STA
SU;STA
SU;DAT
IL
IH
IH
IL
IL
IL
IH
IH
IH
P
F
(VID0 to VID6)
OL
t
R
BUF
(THERM)
S
t
t
LOW
HD;STA
OH
t
HD;DAT
T
A
BATT
= T
I
V
Bit 3 and Bit 4 of Configuration Register 3 = 0
Bit 3 and Bit 4 of Configuration Register 3 = 0
Bit 3 of Configuration Register 3 = 1
Bit 4 of Configuration Register 3 = 1
Bit 3 and Bit 4 of Configuration Register 3 = 1
V
V
See Figure 2
See Figure 2
See Figure 2
See Figure 2
See Figure 2
See Figure 2
See Figure 2
See Figure 2
See Figure 2
See Figure 2
Can be optionally enabled
IL
t
OUT
R
OUT
IN
IN
Figure 2. Serial Bus Timing Diagram
= 0.8 V for a falling edge and V
MIN
= V
= 0
accuracy.
= −3 mA, V
= V
to T
CC
Test Conditions / Comments
CC
BATT
t
SU;DAT
MAX
http://onsemi.com
, +1.2V) is being measured in single−channel mode. See Figure 16 in the Typical
, V
CC
CC
t
HIGH
t
F
= +3.3 V
= V
6
MIN
to V
MAX
IH
S
= 2.0 V for a rising edge.
, unless otherwise noted. (Note 1)
t
SU;STA
CC
≥ 3.3 V and +25°C ≤ T
t
HD;STA
2/3 V
0.65
−1.0
Min
100
2.1
1.7
1.3
0.6
0.6
1.3
0.6
CCP1
A
= 25°C and represent the most likely
t
SU;STO
A
Typ
500
500
0.1
5.0
50
25
≤ +125°C apply.
P
1000
Max
±1.0
+1.0
400
300
0.4
0.8
0.8
0.4
Unit
kHz
mV
mV
mA
mA
mA
ms
pF
ns
ms
ms
ms
ms
ms
ns
ns
ns
V
V
V
V
V
V
V
V