HW-XGI-SCLK-G Xilinx Inc, HW-XGI-SCLK-G Datasheet - Page 14

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HW-XGI-SCLK-G

Manufacturer Part Number
HW-XGI-SCLK-G
Description
MODULE SUPER CLOCK
Manufacturer
Xilinx Inc
Datasheet

Specifications of HW-XGI-SCLK-G

Accessory Type
Clock
For Use With/related Products
ML423, ML521, ML523, ML525
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
References
References
14
LED Representation
Master Reset
Control line register status can be viewed through onboard LEDs, as shown in
page
A master reset option is available using either the onboard momentary switch (SW2) or by
using control line J1, pin 24 (MR - Master Reset). Active with a logic-High, divider
functions are inoperative, and outputs Q0 and NQ0 default to a Low and High state,
respectively.
1.
2.
3.
UG225, ML52x User Guide, Virtex-4 LXT RocketIO Characterization Platform
UG087, ML42x User Guide, Virtex-4 FX RocketIO Characterization Platform
Integrated Device Technology,
Frequency Synthesizer Data Sheet
9.
www.xilinx.com
Inc., 843001-22 FemtoClocks Crystal-to-3.3V LVPECL
Xilinx Generic Interface (XGI) SuperClock Module
UG091 (v1.1) March 2, 2007
Table 1,
R

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