74lcx573 STMicroelectronics, 74lcx573 Datasheet

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74lcx573

Manufacturer Part Number
74lcx573
Description
Octal D-type Latch Non-inverting 3-state With 5v Tolerant Inputs And Outputs
Manufacturer
STMicroelectronics
Datasheet

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DESCRIPTION
The 74LCX573 is a low voltage CMOS OCTAL
D-TYPE
NON-INVERTING fabricated with sub-micron
silicon gate and double-layer metal wiring C
technology. It is ideal for low power and high
speed 3.3V applications; it can be interfaced to 5V
signal environment for both inputs and outputs.
These 8 bit D-Type latch are controlled by a latch
Figure 1: Pin Connection And IEC Logic Symbols
September 2004
5V TOLERANT INPUTS AND OUTPUTS
HIGH SPEED:
t
POWER DOWN PROTECTION ON INPUTS
AND OUTPUTS
SYMMETRICAL OUTPUT IMPEDANCE:
|I
PCI BUS LEVELS GUARANTEED AT 24 mA
BALANCED PROPAGATION DELAYS:
t
OPERATING VOLTAGE RANGE:
V
Retention)
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 573
LATCH-UP PERFORMANCE EXCEEDS
500mA (JESD 17)
ESD PERFORMANCE:
HBM > 2000V (MIL STD 883 method 3015);
MM > 200V
PD
PLH
OH
CC
= 8.0 ns (MAX.) at V
| = I
(OPR) = 2.0V to 3.6V (1.5V Data
t
PHL
LATCH
OL
= 24mA (MIN) at V
OCTAL D-TYPE LATCH NON-INVERTING (3-STATE)
with
WITH 5V TOLERANT INPUTS AND OUTPUTS
3
CC
= 3V
STATE
CC
= 3V
OUTPUT
2
MOS
Table 1: Order Codes
enable input (LE) and an output enable input (OE).
While the LE inputs is held at a high level, the Q
outputs will follow the data input. When the LE is
taken low, the Q outputs will be latched at the logic
level of D input data. While the (OE) input is low,
the 8 outputs will be in a normal logic state (high or
low logic level) and while (OE) is in high level, the
outputs will be in a high impedance state.
It has same speed performance at 3.3V than 5V
AC/ACT family, combined with a lower power
consumption.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
PACKAGE
TSSOP
SOP
SOP
74LCX573
Rev. 5
74LCX573MTR
74LCX573TTR
TSSOP
T & R
1/13

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74lcx573 Summary of contents

Page 1

... SERIES 573 LATCH-UP PERFORMANCE EXCEEDS 500mA (JESD 17) ESD PERFORMANCE: HBM > 2000V (MIL STD 883 method 3015); MM > 200V DESCRIPTION The 74LCX573 is a low voltage CMOS OCTAL D-TYPE LATCH with 3 NON-INVERTING fabricated with sub-micron silicon gate and double-layer metal wiring C technology ideal for low power and high speed 3.3V applications ...

Page 2

... Figure 2: Input And Output Equivalent Circuit Table 2: Pin Description PIN N° SYMBOL NAME AND FUNCTION State Output Enable Input (Active LOW Data Inputs 12, 13, 14 3-State Latch Outputs 15, 16, 17, 18 Latch Enable Input ...

Page 3

... I High or Low Level Output Current ( Operating Temperature op dt/dv Input Rise and Fall Time (note 2) 1) Truth Table guaranteed: 1. from 0. 3. Parameter Parameter = 3.0 to 3.6V 2.7V) CC 74LCX573 Value Unit -0.5 to +7.0 V -0.5 to +7.0 V -0.5 to +7 100 mA 100 ...

Page 4

... Table 6: DC Specifications Symbol Parameter V High Level Input IH Voltage V Low Level Input IL Voltage V High Level Output OH Voltage V Low Level Output OL Voltage I Input Leakage I Current I Power Off Leakage off Current I High Impedance OZ Output Leakage Current I Quiescent Supply CC Current I I incr. per Input ...

Page 5

... OSLH PLHm PLHn OSHL PHLm Test Condition 3 10MHz 74LCX573 Value - °C -55 to 125 °C Min. Max. Min. Max. 1.5 9.0 1.5 9.0 1.5 8.0 1.5 8.0 1.5 9.5 1.5 9.5 1.5 8.5 1.5 8.5 1.5 9.5 1.5 9.5 1.5 8.5 1.5 8.5 1.5 8.5 1.5 8.5 1.5 7.5 1.5 7.5 2.5 2.5 2.5 2.5 1.5 1.5 1.5 1.5 3.3 3.3 3.3 3.3 1.0 1 ...

Page 6

... Figure 4: Test Circuit PLH PHL PZL PLZ PZH PHZ equivalent (includes jig and probe capacitance 500 or equivalent pulse generator (typically OUT Figure 5: Waveform - Propagation Delays, LE Pulse Width Setup And Hold Times (f=1MHz ...

Page 7

... Figure 6: Waveform - Output Enable And Disable Times (f=1MHz; 50% duty cycle) Figure 7: Waveform - Propagation Delay Time (f=1MHz; 50% duty cycle) 74LCX573 7/13 ...

Page 8

... DIM. MIN. A 2.35 A1 0.1 B 0.33 C 0.23 D 12. 10.00 h 0.25 L 0.4 k 0° ddd 8/13 SO-20 MECHANICAL DATA mm. TYP MAX. 2.65 0.30 0.51 0.32 13.00 7.6 1.27 10.65 0.75 1.27 8° 0.100 inch MIN. TYP. 0.093 0.004 0.013 0.009 0.496 0.291 0.050 0.394 0.010 0.016 0° 0016022D MAX. 0.104 0.012 0.020 0.013 0.512 0.299 0.419 0.030 0.050 8° ...

Page 9

... K 0˚ PIN 1 IDENTIFICATION 1 mm. TYP MAX. 1.2 0.15 1 1.05 0.30 0.20 6.5 6.6 6.4 6.6 4.4 4.48 0.65 BSC 8˚ 0.60 0. 74LCX573 inch MIN. TYP. 0.002 0.004 0.031 0.039 0.007 0.004 0.252 0.256 0.244 0.252 0.169 0.173 0.0256 BSC 0˚ 0.018 0.024 0087225C MAX. 0.047 0.006 0.041 0.012 ...

Page 10

... DIM. MIN 12 10.8 Bo 13.2 Ko 3.1 Po 3.9 P 11.9 10/13 Tape & Reel SO-20 MECHANICAL DATA mm. TYP MAX. 330 13.2 30.4 11 13.4 3.3 4.1 12.1 inch MIN. TYP. 12.992 0.504 0.795 2.362 0.425 0.520 0.122 0.153 0.468 MAX. 0.519 1.197 0.433 0.528 0.130 0.161 0.476 ...

Page 11

... Tape & Reel TSSOP20 MECHANICAL DATA DIM. MIN 12 6.8 Bo 6.9 Ko 1.7 Po 3.9 P 11.9 mm. TYP MAX. 330 13.2 0.504 0.795 2.362 22.4 7 0.268 7.1 0.272 1.9 0.067 4.1 0.153 12.1 0.468 74LCX573 inch MIN. TYP. MAX. 12.992 0.519 0.882 0.276 0.280 0.075 0.161 0.476 11/13 ...

Page 12

... Table 10: Revision History Date Revision 15-Sep-2004 5 12/13 Description of Changes Ordering Codes Revision - pag. 1. ...

Page 13

... Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America All other names are the property of their respective owners © 2004 STMicroelectronics - All Rights Reserved STMicroelectronics group of companies www.st.com 74LCX573 13/13 ...

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