AD7671AST Analog Devices Inc, AD7671AST Datasheet
AD7671AST
Specifications of AD7671AST
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AD7671AST Summary of contents
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FEATURES Throughput 1 MSPS (Warp Mode) 800 kSPS (Normal Mode) INL: 2.5 LSB Max ( 0.0038% of Full Scale) 16-Bit Resolution with No Missing Codes S/(N+D Typ @ 250 kHz THD: –100 dB Typ @ 250 kHz ...
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AD7671–SPECIFICATIONS Parameter RESOLUTION ANALOG INPUT Voltage Range Common-Mode Input Voltage Analog Input CMRR Input Impedance THROUGHPUT SPEED Complete Cycle Throughput Rate Time between Conversions Complete Cycle Throughput Rate Complete Cycle Throughput Rate DC ACCURACY Integral Linearity Error No Missing Codes ...
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Parameter POWER SUPPLIES Specified Performance AVDD DVDD OVDD 5 Operating Current AVDD 6 DVDD 6 OVDD 6, 7 Power Dissipation 9 In Power-Down Mode 10 TEMPERATURE RANGE Specified Performance NOTES LSB means least significant bit. With the ± ...
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AD7671 TIMING SPECIFICATIONS (continued) Parameter Refer to Figures 13, 14, 15, and 16 (Parallel Interface Modes) CNVST LOW to DATA Valid Delay (Warp Mode/Normal Mode/Impulse Mode) DATA Valid to BUSY LOW Delay Bus Access Request to DATA Valid Bus Relinquish ...
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... OF 10pF; OTHERWISE, THE LOAD IS 60pF MAXIMUM. L Figure 1. Load Circuit for Digital Interface Timing, SDOUT, SYNC, SCLK Outputs Model Temperature Range AD7671AST –40∞C to +85∞C AD7671ASTRL –40∞C to +85∞C AD7671ACP –40∞C to +85∞C AD7671ACPRL –40∞C to +85∞C 1 EVAL-AD7671CB 2 ...
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AD7671 Pin No. Mnemonic Type Description 1 AGND P Analog Power Ground Pin. 2 AVDD P Input Analog Power Pin. Nominally 44– Connect. 4 BYTESWAP Parallel Mode Selection (8-/16-Bit). When LOW, the LSB is output ...
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Pin No. Mnemonic Type Description 21 D[8] DO When SER/PAR is LOW, this output is used as Bit 8 of the Parallel Port Data Output Bus. or SDOUT When SER/PAR is HIGH, this output, part of the Serial Port, is ...
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AD7671 DEFINITION OF SPECIFICATIONS Integral Nonlinearity Error (INL) Linearity error refers to the deviation of each individual code from a line drawn from “negative full scale” through “positive full scale.” The point used as negative full scale occurs 1/2 LSB ...
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CODE TPC 1. Integral Nonlinearity vs. Code 1.75 1.50 1.25 1.00 0.75 0.50 0.25 0 –0.25 –0.50 –0.75 –1.00 0 16384 32768 CODE TPC 2. Differential ...
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AD7671 1MSPS f –20 SNR = 89.45dB THD = –100.05dB –40 SFDR = 100.49dB SINAD = 89.1dB –60 –80 –100 –120 –140 –160 –180 0 100 200 300 FREQUENCY – kHz TPC 7. FFT Plot 100 95 ...
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C – TPC 13. Typical Delay vs. Load Capacitance C 100000 AVDD, WARP/NORMAL 10000 DVDD, WARP/NORMAL 1000 100 AVDD, IMPULSE 10 0 DVDD, IMPULSE 0.1 OVDD, ALL MODES 0.01 ...
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AD7671 4R IND REF 4R REFGND INC 2R INB R INA INGND CONVERTER OPERATION The AD7671 is a successive approximation analog-to-digital converter based on a charge redistribution DAC. Figure 3 shows the simplified schematic of the ADC. The input analog ...
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Description ± ± Full-Scale Range Least Significant Bit 305.2 mV 152.6 mV FSR – 1 LSB 9.999695 V 4.999847 V 305.2 mV 152.6 mV Midscale + 1 LSB Midscale –305.2 mV ...
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AD7671 Analog Inputs The AD7671 is specified to operate with six full-scale analog input ranges. Connections required for each of the four analog inputs, IND, INC, INB, and INA, and the resulting full-scale ranges are shown in Table I. The ...
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Driver Amplifier Choice Although the AD7671 is easy to drive, the driver amplifier needs to meet at least the following requirements: ∑ The driver amplifier and the AD7671 analog input circuit must be able, together, to settle for a full-scale ...
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AD7671 100 FREQUENCY – kHz Figure 9. PSRR vs. Frequency POWER DISSIPATION In Impulse Mode, the AD7671 automatically reduces its power consumption at the end of each conversion phase. ...
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DIGITAL INTERFACE The AD7671 has a versatile digital interface; it can be interfaced with the host system by using either a serial or parallel interface. The serial interface is multiplexed on the parallel data bus. The AD7671 digital interface also ...
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AD7671 MASTER SERIAL INTERFACE Internal Clock The AD7671 is configured to generate and provide the serial data clock SCLK when the EXT/INT pin is held LOW. It also gener- ates a SYNC signal to indicate to the host when the ...
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CS, RD BUSY SCLK t 31 SDOUT t 16 SDIN t 33 Figure 19. Slave Serial Data Timing for Reading (Read after Convert) the AD7671 provides error correction circuitry that can correct for an improper bit decision made during the ...
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AD7671 CS CNVST BUSY t 3 SCLK SDOUT t 16 Figure 21. Slave Serial Data Timing for Reading (Read Previous Conversion during Convert) To reduce performance degradation due to digital activity, a fast discontinuous clock of at ...
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DVDD AD7671* SER/PAR RDC/SDIN RD EXT/INT SYNC CS SDOUT INVSYNC SCLK CNVST INVSCLK *ADDITIONAL PINS OMITTED FOR CLARITY Figure 23. Interfacing to the ADSP-21065L Using the Serial Master Mode APPLICATION HINTS Layout The AD7671 has very good immunity to noise ...
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AD7671 1.45 1.40 1.35 0.15 SEATING 0.05 PLANE ROTATED 90 CCW 7.00 BSC SQ PIN 1 INDICATOR TOP VIEW 1.00 12 MAX 0.90 0.80 0.20 REF SEATING PLANE OUTLINE DIMENSIONS 48-Lead Low Profile Quad Flat Package [LQFP] (ST-48) Dimensions shown ...
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Revision History Location 4/03—Data Sheet changed from REV REV. B. Changes to PulSAR Selection table . . . . . . . . . . . . . . . . . . . . . . . ...
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