CAT25256 ONSEMI [ON Semiconductor], CAT25256 Datasheet
CAT25256
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CAT25256 Summary of contents
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... SPI Serial CMOS EEPROM Description The CAT25256 is a 256−Kb Serial CMOS EEPROM device internally organized as 32Kx8 bits. This features a 64−byte page write buffer and supports the Serial Peripheral Interface (SPI) protocol. The device is enabled through a Chip Select (CS) input. In addition, the required bus signals are clock input (SCK), data input (SI) and data output (SO) lines ...
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Table 1. ABSOLUTE MAXIMUM RATINGS Operating Temperature Storage Temperature Voltage on any Pin with Respect to Ground (Note 1) Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions ...
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Table 5. A.C. CHARACTERISTICS Symbol Parameter f Clock Frequency SCK t Data Setup Time SU t Data Hold Time H t SCK High Time WH t SCK Low Time WL t HOLD to Output Low (Note 5) ...
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... CAT25256. CS: The chip select input pin is used to enable/disable the CAT25256. When CS is high, the SO output is tri−stated (high impedance) and the device is in Standby Mode (unless an internal write operation is in progress). Every communication ...
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Status Register The Status Register, as shown in Table 8, contains a number of status and control bits. The RDY (Ready) bit indicates whether the device is busy with a write operation. This bit is automatically set to 1 during ...
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... SI SO Dashed Line = mode (1, 1) WRITE OPERATIONS instruction to the CAT25256. Care must be taken to take the CS input high after the WREN instruction, as otherwise the Write Enable Latch will not be properly set. WREN timing is illustrated in Figure 3. The WREN instruction must be sent prior to any WRITE or WRSR instruction. ...
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... WRITE instruction, a 16−bit address and data as shown in Figure 5. Only 15 significant address bits are used by the CAT25256. The rest are don’t care bits, as shown in Table 11. Internal programming will start after the low to high CS transition. During an internal write cycle, all commands, except for RDSR (Read Status Register) will be ignored ...
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Write Status Register The Status Register is written by sending a WRSR instruction according to timing shown in Figure 7. Only bits 2, 3 and 7 can be written using the WRSR command SCK OPCODE ...
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... To read the status register, the host simply sends a RDSR command. After receiving the last bit of the command, the CAT25256 will shift out the contents of the status register on the SO pin (Figure 10). The status register may be read at any time, including during an internal write cycle. While the internal write cycle is in progress, the RDSR command will output the RDY (Ready) bit status only (i ...
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... POR trigger level. This bi−directional POR behavior protects the device against ‘brown−out’ failure following a temporary loss of power. The CAT25256 device powers write disable state and in a low power standby mode. A WREN instruction must be issued prior to any writes to the device. ...
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PIN # 1 IDENTIFICATION D TOP VIEW SIDE VIEW Notes: (1) All dimensions are in millimeters. (2) Complies with JEDEC MS-001. PACKAGE DIMENSIONS PDIP−8, 300 mils CASE 646AA−01 ISSUE A SYMBOL ...
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PIN # 1 IDENTIFICATION TOP VIEW SIDE VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MS-012. PACKAGE DIMENSIONS SOIC 8, 150 mils CASE 751BD−01 ISSUE O SYMBOL ...
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PIN#1 IDENTIFICATION TOP VIEW SIDE VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with EIAJ EDR-7320. PACKAGE DIMENSIONS SOIC−8, 208 mils CASE 751BE−01 ISSUE O SYMBOL ...
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E1 e TOP VIEW SIDE VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MO-153. PACKAGE DIMENSIONS TSSOP8, 4.4x3 CASE 948AL−01 ISSUE O SYMBOL MIN A A1 0.05 A2 ...
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D E PIN #1 IDENTIFICATION TOP VIEW SYMBOL MIN NOM A 0.70 0.75 A1 0.00 0.02 A2 0.45 0.55 A3 0.20 REF b 0.25 0.30 D 2.90 3.00 D2 0.90 1.00 E 4.80 4.90 E2 0.90 1.00 e 0.65 TYP ...
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... All packages are RoHS−compliant (Lead−free, Halogen−free). 10. The standard lead finish is NiPdAu. 11. The device used in the above example is a CAT25256VI−GT3 (SOIC, Industrial Temperature, NiPdAu, Tape & Reel, 3,000/Reel). 12. The SOIC, EIAJ (X) package is only available in 2000 pcs/reel and Matte−Tin lead finish, i.e., CAT25256XI−T2. ...