hef4007ub NXP Semiconductors, hef4007ub Datasheet
hef4007ub
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hef4007ub Summary of contents
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... DATA SHEET For a complete data sheet, please also download: The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC HEF4007UB gates Dual complementary pair and inverter Product specification File under Integrated Circuits, IC04 ...
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... Philips Semiconductors Dual complementary pair and inverter DESCRIPTION The HEF4007UB is a dual complementary pair and an inverter with access to each device. It has three n-channel and three p-channel enhancement mode MOS transistors. Fig.2 Pinning diagram. HEF4007UBP(N): 14-lead DIL; plastic (SOT27-1) HEF4007UBD(F): 14-lead DIL; ceramic (cerdip) ...
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... TYPICAL FORMULA FOR 4500 000 000 Product specification HEF4007UB TYPICAL EXTRAPOLATION MAX. FORMULA (0,55 ns/pF (0,23 ns/pF (0,16 ns/pF (0,55 ns/pF (0,23 ns/pF (0,16 ns/pF) C 120 ...
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... V D functions of input voltage; V Fig.4 Typical drain current I and output voltage V D functions of input voltage; V Fig.5 Typical drain current I D functions of input voltage Product specification HEF4007UB gates amb amb ...
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... Philips Semiconductors Dual complementary pair and inverter APPLICATION INFORMATION Some examples of applications for the HEF4007UB are: High input impedance amplifiers Linear amplifiers (Crystal) oscillators High-current sink and source drivers High impedance buffers. Fig.6 Voltage gain ( function of supply o i voltage. ...
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... A: average, B: average + average where ‘s’ is the observed standard deviation. Fig.10 Typical forward transconductance g January 1995 = di / constant (see also graph Fig.10 function of the supply voltage Product specification HEF4007UB gates = 25 C. amb ...
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... Philips Semiconductors Dual complementary pair and inverter Figures show some applications in which the HEF4007UB is used. January 1995 Fig.11 4 MHz crystal oscillator. Fig.12 High current sink driver. Fig.13 High current source driver. 7 Product specification HEF4007UB gates ...
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... Rules for maintaining electrical isolation between transistors and monolithic substrate: Pin number 14 must be maintained at the most positive (or equally positive) potential with respect to any other pin of the HEF4007UB. Pin number 7 must be maintained at the most negative (or equally negative) potential with respect to any other pin of the HEF4007UB. ...