ics9db104 Integrated Device Technology, ics9db104 Datasheet
ics9db104
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ics9db104 Summary of contents
Page 1
... Pin Configuration VDD 1 SRC_IN 2 SRC_IN# 3 GND 4 VDD 5 DIF_1 6 DIF_1# 7 OE_1 8 DIF_2 9 DIF_2# 10 VDD 11 BYPASS#/PLL 12 SCLK 13 SDATA 14 28-pin SSOP & TSSOP ICS9DB104 28 VDDA 27 GNDA 26 IREF 25 GND 24 VDD 23 DIF_6 22 DIF_6# 21 OE_6 20 DIF_5 19 DIF_5# 18 VDD 17 HIGH_BW# 16 SRC_STOP# 15 PD# ...
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... This pin establishes the reference current for the differential current- mode output pairs. This pin requires a fixed precision resistor tied to ground in order to establish the appropriate current. 475 ohms is the standard value. Ground pin for the PLL core. 3.3V power for the PLL core. 2 ICS9DB104 ...
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... ICS9DB104 follows the Intel DB400 Differential Buffer Specification. This buffer provides four SRC clocks for PCI-Express, next generation I/O devices. ICS9DB104 is driven by a differential input pair from a CK409/CK410 main clock generator, such as the ICS952601 or ICS954101. ICS9DB104 can run at speeds up to 200MHz. It provides ouputs meeting tight cycle-to-cycle jitter (50ps) and output-to-output skew (50ps) requirements. ...
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... DD input clock stabilization or de- assertion of PD# to 1st clock Triangular Modulation DIF output enable after SRC_Stop# de-assertion DIF output enable after PD# de-assertion Fall time of PD# and SRC_STOP# Rise time of PD# and SRC_STOP# 4 ICS9DB104 Units ° C °C °C V TYP MAX UNITS NOTES ...
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... Measurement from differential wavefrom V = 50% T PLL mode, Measurement from differential wavefrom BYPASS mode as additive jitter = 2.32mA and V REF OH REF OH 5 ICS9DB104 MIN TYP MAX UNITS Ω 3000 660 850 mV -150 150 1150 mV -300 250 550 mV 140 mV 0 ppm 4 ...
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... Integrated Circuit Systems, Inc. General SMBus serial interface information for the ICS9DB104 How to Write: • Controller (host) sends a start bit. • Controller (host) sends the write address DC • ICS clock will acknowledge • Controller (host) sends the begining byte location = N • ICS clock will acknowledge • ...
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... Control Type 0 Function Reserved RW Reserved Output RW Free-run Stoppable Control Output RW Free-run Stoppable Control Reserved RW Reserved Reserved RW Reserved Output RW Free-run Stoppable Control Output RW Free-run Stoppable Control Reserved RW Reserved 7 ICS9DB104 1 PWD Hi ZDB PWD 1 Enable 1 Enable Enable 1 Enable 1 1 ...
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... Reserved Device Reserved Device Reserved Device Reserved Control Type 0 Function RW - Writing this register RW - configures RW - how many RW - bytes will read RW - back ICS9DB104 1 PWD PWD - PWD ...
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... SRC_IN clocks until the time that stable clocks are output from the device (PLL Locked). If the PD# drive mode bit is set to ‘1’, all the DIF outputs must driven to a voltage of >200 mV within 300 ms of PD# de-assertion. PWRDWN# DIF DIF# 0767E—12/14/07 (Not recommended for new designs) and DIF# tri-stated. If the PD# drive mode bit is REF Tstable <1mS Tdrive_PwrDwn# <300uS, >200mV 9 ICS9DB104 ...
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... DIF (Stoppable) DIF# (Stoppable) SRC_STOP_2 (SRC_Stop =Tristate Driven) SRC_Stop# PWRDWN# DIF (Free Running) DIF# (Free Running) DIF (Stoppable) DIF# (Stoppable) 0767E—12/14/07 (Not recommended for new designs) DIF# is not driven, but pulled low by the termination. When the REF. 1mS 1mS 10 ICS9DB104 ...
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... SRC_STOP_3 (SRC_Stop = Driven Tristate) SRC_Stop# PWRDWN# DIF (Free Running) DIF# (Free Running) DIF (Stoppable) DIF# (Stoppable) SRC_STOP_4 (SRC_Stop = Tristate Tristate) SRC_Stop# PWRDWN# DIF (Free Running) DIF# (Free Running) DIF (Stoppable) DIF# (Stoppable) 0767E—12/14/07 (Not recommended for new designs) 1mS 1mS 11 ICS9DB104 ...
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... Lead Free, RoHS Compliant (Optional) Package Type F = SSOP Revision Designator (will not correlate with datasheet revision) Device Type (consists digit numbers) Prefix ICS = Standard Device ICS9DB104 209 mil SSOP In Millimeters In Inches COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN -- 2 ...
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... Lead Free, RoHS Compliant (Optional) Package Type G = TSSOP Revision Designator (will not correlate with datasheet revision) Device Type (consists digit numbers) Prefix ICS = Standard Device 13 ICS9DB104 4.40 mm. Body, 0.65 mm. Pitch TSSOP (173 mil) (25.6 mil) In Millimeters In Inches COMMON DIMENSIONS COMMON DIMENSIONS MIN ...
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... Integrated Circuit Systems, Inc. Revision History Rev. Issue Date Description D 10/26/05 Updated LF Ordering Information LF. E 12/14/07 Updated SMBus serial Interface Information. 0767E—12/14/07 (Not recommended for new designs) 14 ICS9DB104 Page # 12 ...