ics9fg1901 Integrated Device Technology, ics9fg1901 Datasheet
ics9fg1901
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ics9fg1901 Summary of contents
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... It is recommended that Byte 2, bit 6 be toggled from and back to 1, the first time VDDA is applied. This ensures proper initialization of the device. Pin Configuration ICS9FG1901 72-pin MLF Other names and brands may be claimed as the property of others. ICS9FG1901 CLK_IN (CPU FSB) DIF_(18:0) MHz MHz 100 <= CLK_IN < 200 CLK_IN ...
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... Active low input for enabling DIF pair tri-state outputs enable outputs 0.7V differential true clock output 0.7V differential complement clock output IN SMBus address bit 0 (LSB) IN SMBus address bit 1 2 ICS9FG1901 DESCRIPTION ...
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... SMBus address bit 2. When Low, the part operates as a fanout buffer with the PLL bypassed. When High, the part operates as a zero-delay buffer (ZDB) with the PLL operating fanout mode (PLL bypassed ZDB mode (PLL used) 3 ICS9FG1901 ...
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... Systems, Inc. General Description The ICS9FG1901 follows the Intel DB1900G Differential Buffer Specification. This buffer provides 19 output clocks for CPU Host Bus, PCI-Express, or Fully Buffered DIMM applications. The outputs are configured with two groups. Both groups, DIF_(16:0) and DIF_(18:17) can be equal to or have a gear ratio to the input clock. A differential CPU clock from a CK410 or CK410B main clock generator, such as the ICS954101 or ICS932S401, drives the ICS9FG1901 ...
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... Integrated Circuit Systems, Inc. ICS9FG1901 Programmable Gear Ratios SMBus Byte 0 Input Output (m) ( ...
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... V DD Logic Inputs Output pin capacitance From V Power-Up or valid input DD clock, whichever comes last Triangular Modulation Maximum input voltage @ I PULLUP (Max VIL - 0.15) to (Min VIH + 0.15) (Min VIH + 0.15) to (Max VIL - 0.15) 6 ICS9FG1901 Units V V ° C °C °C V MIN TYP MAX UNITS NOTES 0 ...
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... PLL Mode pdpll t Bypass Mode pdbyp PLL mode, t from differential wavefrom jcyc-cyc Bypass mode as additive jitter = and =50Ω. OH REF ICS9FG1901 MIN TYP MAX UNITS NOTES Ω 3000 660 750 850 mV -150 150 1150 mV -300 250 550 mV 140 ...
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... Guaranteed by design and characterization, not 100% tested in production. 0962E—01/02/07 Conditions (HIGH_BW (HIGH_BW (HIGH_BW HIBW (HIGH_BW LOBW (including PLL BW 1.5-22 MHz 0.54, θ PCIe1 Td=10 ns, Ftrk=1.5 MHz ) (including PLL BW 11 0.54, θ FBD Td=5 ns, Ftrk=0.2 MHz) 8 ICS9FG1901 Min Typical Max Units Notes 0 1 2 2,8 2 2.3 ...
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... SMB_A(2:0) = 100 OR SMB Adr: D8 9FG1901 9FG1201/2 (DB1200G) SMB_A(2:0) = 101 OR SMB Adr: DA 9FG1901 9FG1201/2 (DB1200G) SMB_A(2:0) = 110 OR SMB Adr: DC 9FG1901 9FG1201/2 (DB1200G) SMB_A(2:0) = 111 OR SMB Adr: DE 9FG1901 9FG1201/2 (DB1200G) 9 ICS9FG1901 SMB Adr: D2 954101 OR 932S401 (CK410/410B) SMB Adr 9DB104/108 (DB400/800) ...
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... Output Control Control Function Readback - OE9# Input Readback - OE8# Input Readback - OE7# Input Readback - OE6# Input Readback - OE5# Input Readback - HIGH_BW ICS9FG1901 Type Gear Ratio 1:1 RW Gear Ratio 1:1 RW See ICS9FG1901 RW Programmable Gear Ratios RW Table RW RW Type Hi-Z Enable RW Hi-Z Enable RW Hi-Z Enable RW ...
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... VENDOR ID Control Function Device ID 7 (MSB) Device ID 6 Device ID 5 Device ID 4 Device ID 3 Device ID 2 Device ID 1 Device ID 0 Control Function Writing to this register configures how many bytes will be read back. 11 ICS9FG1901 Type Readback R Readback R Readback R Readback R Readback R Readback ...
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... RESERVED RESERVED RESERVED RESERVED Control Function Gearing PLL and 1:1 PLL M/N Programming Enable RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED Control Function N Divider Prog bit 8 N Divider Prog bit 9 M Divider Programming bit (5:0) 12 ICS9FG1901 Type Readback RW Hi-Z Enable RW Hi-Z Enable RW Hi-Z Enable RW Hi-Z Enable RW Hi-Z Enable ...
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... PLL 1 Output Divider RW Control Function Type RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED Control Function Type RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED 13 ICS9FG1901 0 1 PWD PWD See Output Divider Table X ...
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... Type Divider Programming b(7: Control Function Type RESERVED RESERVED RESERVED RESERVED PLL 2 Output Divider RW PLL 2 Output Divider RW PLL 2 Output Divider RW PLL 2 Output Divider RW 14 ICS9FG1901 0 1 PWD PWD PWD ...
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... RESERVED RESERVED RESERVED RESERVED RESERVED Test Function ICS ONLY TEST ICS ONLY TEST ICS ONLY TEST ICS ONLY TEST ICS ONLY TEST ICS ONLY TEST ICS ONLY TEST ICS ONLY TEST 15 ICS9FG1901 Type 0 1 Type Test Result RW Reserved RW Reserved RW Reserved RW Reserved RW ...
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... Designation for tape and reel packaging Lead Free, RoHS Compliant (Optional) Package Type K = MLF Revision Designator (will not correlate with datasheet revision) Device Type (consists digit numbers) Prefix ICS Standard Device 16 ICS9FG1901 DIMENSIONS ICS 72L SYMBOL TOLERANCE ...
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... Updated TBD to actual values. 2. Added PLL BW and Peaking Table. 3. Updated Skew specs. C 6/14/2006 4. Updated Paddle Dimensions. D 8/17/2006 Final Release. 1. Added Output Dividers to Bytes 13 and 19 for Rev H devices. 2. Changed PLL1 and PLL2 naming to 1:1 and Gearing PLL E 1/2/2007 0962E—01/02/07 Various Various 17 ICS9FG1901 Page # ...