IDT72T72115 Integrated Device Technology, IDT72T72115 Datasheet
IDT72T72115
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IDT72T72115 Summary of contents
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... IDT72T7295 32,768 x 72 IDT72T72105 ⎯ ⎯ ⎯ ⎯ ⎯ 65,536 x 72 IDT72T72115 ⎯ ⎯ ⎯ ⎯ ⎯ 131,072 x 72 • • • • • 225 MHz Operation of Clocks • • • • • User selectable HSTL/LVTTL Input and/or Output • ...
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IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync™ ™ ™ ™ ™ 72-BIT FIFO 16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72 PIN CONFIGURATION A1 BALL PAD CORNER A V D60 D61 D63 D66 CC B D59 D58 D62 D64 D67 ...
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IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync™ ™ ™ ™ ™ 72-BIT FIFO 16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72 DESCRIPTION: The IDT72T7285/72T7295/72T72105/72T72115 are exceptionally deep, extremely high speed, CMOS First-In-First-Out (FIFO) memories with clocked read and write controls ...
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IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync™ ™ ™ ™ ™ 72-BIT FIFO 16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72 DESCRIPTION (CONTINUED) The device can be configured with different input and output bus widths as shown in Table 1. ...
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IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync™ ™ ™ ™ ™ 72-BIT FIFO 16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72 WRITE CLOCK (WCLK/WR) WRITE ENABLE (WEN) WRITE CHIP SELECT (WCS) (x72, x36, x18) DATA IN (D SERIAL CLOCK (SCLK) ...
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IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync™ ™ ™ ™ ™ 72-BIT FIFO 16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72 PIN DESCRIPTION Symbol Name I/O TYPE (1) ASYR Asynchronous LVTTL Read Port INPUT ASYW (1) Asynchronous LVTTL Write Port ...
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IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync™ ™ ™ ™ ™ 72-BIT FIFO 16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72 PIN DESCRIPTION (CONTINUED) Symbol Name I/O TYPE PAE HSTL-LVTTL PAE goes LOW if the number of words in the ...
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IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync™ ™ ™ ™ ™ 72-BIT FIFO 16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72 PIN DESCRIPTION (CONTINUED) Symbol Name I/O TYPE TRST HSTL-LVTTL TRST is an asynchronous reset pin for the JTAG controller. ...
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IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync™ ™ ™ ™ ™ 72-BIT FIFO 16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72 ABSOLUTE MAXIMUM RATINGS Symbol Rating V Terminal Voltage TERM with respect to GND T Storage Temperature STG I DC ...
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... Industrial temperature range product for the 5ns speed grade is available as a standard device. All other speed grades are available by special order. — SYNCHRONOUS TIMING (1) = 2.5V ± 5 -40°C to +85° Commercial Com’l & Ind’l IDT72T7285L4-4 IDT72T7285L5 IDT72T7295L4-4 IDT72T7295L5 IDT72T72105L4-4 IDT72T72105L5 IDT72T72105L6-7 IDT72T72105L10 IDT72T72115L4-4 IDT72T72115L5 IDT72T72115L6-7 IDT72T72115L10 Min. Max. Min. Max. — 225 — 200 0.6 3.4 0.6 3.6 4.44 — 5 — 2.0 — ...
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... COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES Com’l & Ind’l Commercial IDT72T7285L5 IDT72T7285L6-7 IDT72T7285L10 IDT72T7295L5 IDT72T7295L6-7 IDT72T7295L10 IDT72T72105L5 IDT72T72105L6-7 IDT72T72105L10 IDT72T72115L5 IDT72T72115L6-7 IDT72T72115L10 Min. Max. Min. Max. Min. — 83 — 66 — 0.6 10 0.6 12 0.6 12 — 15 — — ...
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IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync™ ™ ™ ™ ™ 72-BIT FIFO 16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72 HSTL 1.5V AC TEST CONDITIONS Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels NOTE: ...
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IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync™ ™ ™ ™ ™ 72-BIT FIFO 16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72 OUTPUT ENABLE & DISABLE TIMING Output Enable OE Output V CC Normally 2 LOW Output V CC Normally 2 ...
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... IDT72T7285, (32,769-m) writes for the IDT72T7295, (65,537-m) writes for the IDT72T72105 and (131,073-m) writes for the IDT72T72115, where m is the full offset value. The default setting for these values are stated in the footnote of Table 2. When the FIFO is full, the Input Ready (IR) flag will go HIGH, inhibiting further write operations ...
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IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync™ ™ ™ ™ ™ 72-BIT FIFO 16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72 TABLE 2 — DEFAULT PROGRAMMABLE FLAG OFFSETS IDT72T7285,72T7295,72T72105,72T72115 *LD FSEL1 FSEL0 ...
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... PAF HF PAE EF IDT72T72115 ( (n+1) to 65,536 65,537 to (131,072-(m+1)) (131,072-m) to 131,071 131,072 PAF HF PAE OR IR IDT72T72115 n (n+2) to 65,537 65,538 to (131,073-(m+1 (131,073-m) to 131,072 131,073 ...
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... Full Offset (MSB) Serial shift into registers: 28 bits for the IDT72T7285 30 bits for the IDT72T7295 32 bits for the IDT72T72105 34 bits for the IDT72T72115 1 bit for each rising SCLK edge Starting with Empty Offset (LSB) Ending with Full Offset (MSB Operation ...
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... Non-Interspersed Parity Interspersed Parity D/Q0 Non-Interspersed Parity 1 Interspersed 3 2 Parity # of Bits Used: 14 bits for the IDT72T7285 15 bits for the IDT72T7295 16 bits for the IDT72T72105 17 bits for the IDT72T72115 Note: All unused input bits are don’t care. 5994 drw07 ...
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... SCLK rising edge, starting with the Empty Offset LSB and ending with the Full Offset MSB. A total of 28 bits for the IDT72T7285, 30 bits for the IDT72T7295, 32 bits for the IDT72T72105 and 34 bits for the IDT72T72115. See Figure 20, Serial Loading of Programmable Flag Registers, for the timing diagram for this mode ...
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IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync™ ™ ™ ™ ™ 72-BIT FIFO 16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72 Once a marked location has been set (and the device is still in retransmit mode, MARK is HIGH), a ...
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... Note, for the IDT72T7285/72T7295/72T72105, there must be a minimum of 128 bytes of data between the write pointer and read pointer when the MARK is asserted. For the IDT72T72115, there must be a minimum of 256 bytes of data between the write pointer and read pointer when the MARK is asserted ...
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IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync™ ™ ™ ™ ™ 72-BIT FIFO 16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72 marked location. During retransmit mode write operations to the device may continue without hindrance. FIRST WORD FALL THROUGH/SERIAL IN ...
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IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync™ ™ ™ ™ ™ 72-BIT FIFO 16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72 into a high impedance state. During Master or a Partial Reset the OE is the only input that can ...
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... FIFO. The PAF will go LOW after (16,384-m) writes for the IDT72T7285, (32,768-m) writes for the IDT72T7295, (65,536-m) writes for the IDT72T72105 and (131,072-m) writes for the IDT72T72115. The offset “m” is the full offset COMMERCIAL AND INDUSTRIAL value. The default setting for this value is stated in the footnote of Table 3. ...
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IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync™ ™ ™ ™ ™ 72-BIT FIFO 16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72 ECHO READ CLOCK (ERCLK) The Echo Read Clock output is provided in both HSTL and LVTTL mode, selectable via ...
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IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync™ ™ ™ ™ ™ 72-BIT FIFO 16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72 BYTE ORDER ON INPUT PORT: BYTE ORDER ON OUTPUT PORT ...
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IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync™ ™ ™ ™ ™ 72-BIT FIFO 16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72 BYTE ORDER ON INPUT PORT: BYTE ORDER ON OUTPUT PORT ...
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... Figure 6. Standard JTAG Timing JTAG AC ELECTRICAL CHARACTERISTICS ( 2.5V Parameter IDT72T7285 JTAG Clock Input Period t IDT72T7295 JTAG Clock HIGH IDT72T72105 IDT72T72115 JTAG Clock Low Min. Max. Units JTAG Clock Rise Time - 20 ns JTAG Clock Fall Time JTAG Reset ...
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IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync™ ™ ™ ™ ™ 72-BIT FIFO 16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72 JTAG INTERFACE Five additional pins (TDI, TDO, TMS, TCK and TRST) are provided to support the JTAG boundary scan ...
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IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync™ ™ ™ ™ ™ 72-BIT FIFO 16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 Input = TMS NOTES: 1. Five consecutive TCK cycles with TMS = 1 will reset the TAP. ...
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... Manufacturer ID field. For the IDT72T7285/72T7295/72T72105/72T72115, the Part Number field contains the following values: Device Part# Field IDT72T7285 IDT72T7295 IDT72T72105 IDT72T72115 31(MSB Version (4 bits) Part Number (16-bit) Manufacturer ID (11-bit) 0X0 0X33 IDT72T7285/95/105/115 JTAG Device Identification Register ...
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IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync™ ™ ™ ™ ™ 72-BIT FIFO 16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72 MRS t RSS REN t RSS WEN t RSS FWFT/SI t RSS LD t RSS FSEL0, FSEL1 t RSS ...
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IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync™ ™ ™ ™ ™ 72-BIT FIFO 16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72 PRS t RSS REN t RSS WEN t RSS RT t RSS SEN EF/OR FF/IR PAE PAF, HF (1) ...
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IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync™ ™ ™ ™ ™ 72-BIT FIFO 16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 WRITE WCLK 1 (1) t SKEW1 WEN RCLK t ENS t ENH ...
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IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync™ ™ ™ ™ ™ 72-BIT FIFO 16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72 RCLK t ENS REN t ENS t ENH RCS RCSLZ LAST DATA ...
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IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync™ ™ ™ ™ ™ 72-BIT FIFO 16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72 COMMERCIAL AND INDUSTRIAL 36 TEMPERATURE RANGES ...
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IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync™ ™ ™ ™ ™ 72-BIT FIFO 16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72 COMMERCIAL AND INDUSTRIAL 37 TEMPERATURE RANGES ...
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IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync™ ™ ™ ™ ™ 72-BIT FIFO 16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72 COMMERCIAL AND INDUSTRIAL 38 TEMPERATURE RANGES ...
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IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync™ ™ ™ ™ ™ 72-BIT FIFO 16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72 COMMERCIAL AND INDUSTRIAL 39 TEMPERATURE RANGES ...
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IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync™ ™ ™ ™ ™ 72-BIT FIFO 16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72 COMMERCIAL AND INDUSTRIAL 40 TEMPERATURE RANGES ...
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IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync™ ™ ™ ™ ™ 72-BIT FIFO 16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72 COMMERCIAL AND INDUSTRIAL 41 TEMPERATURE RANGES ...
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... SEN t t LDS LD t SDS BIT 1 SI NOTE for the IDT72T7285 for the IDT72T7295 for the IDT72T72105 for the IDT72T72115. Figure 20. Serial Loading of Programmable Flag Registers (IDT Standard and FWFT Modes) WCLK LD WEN NOTE: 1. This timing diagram illustrates programming with an input bus width of 72 bits. ...
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... D = maximum FIFO depth. In IDT Standard mode 16,384 for the IDT72T7285, 32,768 for the IDT72T7295, 65,536 for the IDT72T72105 and 131,072 for the IDT72T72115. In FWFT mode 16,385 for the IDT72T7285, 32,769 for the IDT72T7295, 65,537 for the IDT72T72105 and 131,073 for the IDT72T72115. ...
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... D = maximum FIFO Depth. In IDT Standard Mode: D= 16,384 for the IDT72T7285, 32,768 for the IDT72T7295, 65,536 for the IDT72T72105 and 131,072 for the IDT72T72115. In FWFT Mode: D= 16,385 for the IDT72T7285, 32,769 for the IDT72T7295, 65,537 for the IDT72T72105 and 131,073 for the IDT72T72115. ...
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... NOTES IDT Standard mode maximum FIFO depth 16,384 for the IDT72T7285, 32,768 for the IDT72T7295, 65,536 for the IDT72T72105 and 131,072 for the IDT72T72115 FWFT mode maximum FIFO depth 16,385 for the IDT72T7285, 32,769 for the IDT72T7295, 65,537 for the IDT72T72105 and 131,073 for the IDT72T72115. ...
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IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync™ ™ ™ ™ ™ 72-BIT FIFO 16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72 COMMERCIAL AND INDUSTRIAL 46 TEMPERATURE RANGES ...
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IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync™ ™ ™ ™ ™ 72-BIT FIFO 16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72 WCLK t ENS WEN n+1 n+2 t SKEW1 ...
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IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync™ ™ ™ ™ ™ 72-BIT FIFO 16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72 RCLK REN FFA NOTE LOW, ...
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IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync™ ™ ™ ™ ™ 72-BIT FIFO 16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 Write WCLK 1 WEN SKEW t CYL Last Word W X ...
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IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync™ ™ ™ ™ ™ 72-BIT FIFO 16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 CYC t t CYH CYL Last Word in O/P Register ...
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IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync™ ™ ™ ™ ™ 72-BIT FIFO 16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72 OPTIONAL CONFIGURATIONS WIDTH EXPANSION CONFIGURATION Word width may be increased simply by connecting together the control signals of multiple ...
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... The IDT72T7285 can easily be adapted to applications requiring depths greater than 16,384, 32,768 for the IDT72T7295, 65,536 for the IDT72T72105 and 131,072 for the IDT72T72115 with an 72-bit bus width. In FWFT mode, the FIFOs can be connected in series (the data outputs of one FIFO connected to the data inputs of the next) with no external logic necessary ...
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ORDERING INFORMATION IDT XXXXX X XX Device Type Power Speed NOTES: 1. Industrial temperature range product for 5ns speed grade is available as a standard device. All other speed grades are available by special order. 2. Green parts available. For ...