IDT72V291 Integrated Device Technology, IDT72V291 Datasheet
IDT72V291
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IDT72V291 Summary of contents
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... SuperSync devices has been eliminated on this SuperSync family INPUT REGISTER RAM ARRAY 65,536 x 9 131,072 x 9 OUTPUT REGISTER IDT72V281 IDT72V291 LD SEN OFFSET REGISTER FF/IR PAF EF/OR FLAG PAE LOGIC HF FWFT/SI READ POINTER READ RT CONTROL LOGIC RCLK ...
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IDT72V281/72V291 3.3V CMOS SUPERSYNC FIFO 65,536 x 9 and 131,072 x 9 DESCRIPTION (Continued) SuperSync FIFOs are particularly appropriate for network, video, telecommu- nications, data communications and other applications that need to buffer large amounts of data. The input port ...
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IDT72V281/72V291 3.3V CMOS SUPERSYNC FIFO 65,536 x 9 and 131,072 x 9 DESCRIPTION (Continued) In FWFT mode, the first word written to an empty FIFO is clocked directly to the data output lines after three transitions of the RCLK signal. ...
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IDT72V281/72V291 3.3V CMOS SUPERSYNC FIFO 65,536 x 9 and 131,072 x 9 PIN DESCRIPTION Symbol Name D –D Data Inputs 0 8 MRS Master Reset PRS Partial Reset RT Retransmit FWFT/SI First Word Fall Through/Serial In WCLK Write Clock WEN ...
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... Ind’l) 2.0 — Input Low Voltage (Com’l & Ind’l) — — Operating Temperature 0 — Commercial Operating Temperature -40 Industrial IDT72V281L IDT72V291L Com’l & Ind’l ( 10, 15 CLK Min. Max. –1 1 –10 10 2.4 — — 0.4 — ...
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... GND to 3.0V 3ns 1.5V 1.5V See Figure 2 6 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES Com’l & Ind’l (2) Commercial IDT72V281L15 IDT72V281L20 IDT72V291L15 IDT72V291L20 Min. Max. Min. Max. — 66.7 — — 20 — 6 — 8 — 6 — 8 — ...
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... FIFO will cause the PAF to go LOW. Again reads are performed, the PAF will go LOW after (65,537-m) writes for the IDT72V281 and (131,073-m) writes for the IDT72V291, where m is the full offset value. The default setting for this value is stated in the footnote of Table 2. ...
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IDT72V281/72V291 3.3V CMOS SUPERSYNC FIFO 65,536 x 9 and 131,072 addition to loading offset values into the FIFO, it also possible to read the current offset values only possible to read offset values via parallel ...
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IDT72V281/72V291 3.3V CMOS SUPERSYNC FIFO 65,536 x 9 and 131,072 x 9 72V281 (65,536 x 9›BIT EMPTY OFFSET (LSB) REGISTER DEFAULT VALUE 7FH LOW at Master Reset FFH HIGH at Master Reset ...
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... SI input are written, one bit for each WCLK rising edge, starting with the Empty Offset LSB and ending with the Full Offset MSB. A total of 32 bits for the IDT72V281 and 34 bits for the IDT72V291. See Figure 13, Serial Loading of Programmable Flag Registers, for the timing diagram for this mode ...
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... words should have been written into the FIFO between Reset (Master or Partial) and the time of Retransmit setup 65,536 for the IDT72V281 and D = 131,072 for the IDT72V291 in IDT Standard mode. In FWFT mode 65,537 for the IDT72V281 and D = 131,073 for the IDT72V291 ...
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IDT72V281/72V291 3.3V CMOS SUPERSYNC FIFO 65,536 x 9 and 131,072 x 9 SIGNAL DESCRIPTION INPUTS: DATA Data inputs for 9-bit wide data. CONTROLS: MRS MRS) MRS MRS MASTER RESET (MRS A Master Reset ...
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... If no reads are performed after a reset (either MRS or PRS), IR will go HIGH after D writes to the FIFO (D = 65,537 for the IDT72V281 and after the valid WCLK cycle. 131,073 for the IDT72V291) See Figure 9, Write Timing (FWFT Mode), for the relevant timing information. SKEW The IR status not only measures the contents of the FIFO memory, but also counts the presence of a word in the output register ...
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... PAF will go LOW after ( words are written to the FIFO. The PAF will go LOW after (65,536-m) writes for the IDT72V281 and (131,072-m) writes for the IDT72V291. The offset “m” is the full offset value. The default setting for this value is stated in the footnote of Table 1 ...
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IDT72V281/72V291 3.3V CMOS SUPERSYNC FIFO 65,536 x 9 and 131,072 x 9 MRS REN WEN t FWFT FWFT/ SEN EF/OR FF/IR PAE PAF RSS t RSS t RSS ...
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IDT72V281/72V291 3.3V CMOS SUPERSYNC FIFO 65,536 x 9 and 131,072 x 9 PRS REN WEN RT SEN EF/OR FF/IR PAE PAF RSS t RSS t RSS t RSS t RSF ...
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IDT72V281/72V291 3.3V CMOS SUPERSYNC FIFO 65,536 x 9 and 131,072 WRITE WCLK 1 (1) t SKEW1 WEN RCLK t t ENS ENH REN DATA ...
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IDT72V281/72V291 3.3V CMOS SUPERSYNC FIFO 65,536 x 9 and 131,072 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES ...
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IDT72V281/72V291 3.3V CMOS SUPERSYNC FIFO 65,536 x 9 and 131,072 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES ...
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... FIFO after Master Reset more than may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore, FF will be HIGH throughout the Retransmit setup procedure 65,536 for the IDT72V281 and 131,072 for the IDT72V291 goes HIGH at 60ns + 1 RCLK cycle + t . ...
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... OR goes LOW at 60ns + 2 RCLK cycles + t . REF WCLK t ENS SEN t LDS BIT 0 SI NOTE for the IDT72V281 and for the IDT72V291. Figure 13. Serial Loading of Programmable Flag Registers (IDT Standard and FWFT Modes x+1 t SKEW2 ENH t REF t ...
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... ENS ENH REN DATA IN OUTPUT REGISTER 0 7 NOTE LOW Figure 17. Parallel Read of Programmable Flag Registers (IDT Standard and FWFT Modes) for the IDT72V291 TM t LDH t ENH t DH PAE OFFSET PAF OFFSET (MSB) (LSB) PAE OFFSET PAF OFFSET ...
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... REN NOTES: 1. For IDT Standard mode maximum FIFO depth 65,536 for the IDT72V281 and 131,072 for the IDT72V291. 2. For FWFT mode maximum FIFO depth 65,537 for the IDT72V281 and 131,073 for the IDT72V291. Figure 20. Half-Full Flag Timing (IDT Standard and FWFT Modes) ...
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... DEPTH EXPANSION CONFIGURATION (FWFT MODE ONLY) The IDT72V281 can easily be adapted to applications requiring depths greater than 65,536 and 131,072 for the IDT72V291 with a 9-bit bus width. In FWFT mode, the FIFOs can be connected in series (the data outputs of one FIFO connected to the data inputs of the next) with no external logic necessary ...
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IDT72V281/72V291 3.3V CMOS SUPERSYNC FIFO 65,536 x 9 and 131,072 x 9 FWFT/SI FWFT/SI WRITE CLOCK WCLK WRITE ENABLE WEN IDT INPUT READY IR 72V281 72V291 n DATA IN Dn Figure 22. Block Diagram of 131,072 x 9 and 262,144 ...
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ORDERING INFORMATION IDT XXXXX X XX Device Type Power Speed NOTE: 1. Industrial temperature range product for the 15ns speed grade is available as a standard device. DATASHEET DOCUMENT HISTORY 04/24/2001 pgs and 26. CORPORATE HEADQUARTERS 6024 ...