is43r16160 Integrated Silicon Solution, Inc., is43r16160 Datasheet

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is43r16160

Manufacturer Part Number
is43r16160
Description
32mx8, 16mx16 256mb Synchronous Dram
Manufacturer
Integrated Silicon Solution, Inc.
Datasheet

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IS43R16160
32Mx8, 16Mx16
256Mb Synchronous DRAM
FEATURES:
ADDRESS TABLE
Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without
notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the
latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc.
Rev. 00A
09/10/08
Parameter
Configuration
Bank Address Pins
Autoprecharge Pins
Row Addresses
Column Addresses
Refresh Count
V
Double data rate architecture ; two data transfers
per clock cycle.
Bidirectional , data strobe (DQS) is transmitted/
received with data
Differential clock input (CLK and /CLK)
DLL aligns DQ and DQS transitions with CLK
transitions edges of DQS
Commands entered on each positive CLK edge;
Data and data mask referenced to both edges of
DQS
4 bank operation controlled by BA0 , BA1
(Bank Address)
/CAS latency -2.0 / 2.5 / 3.0 (programmable) ;
Burst length -2 / 4 / 8 (programmable)
Burst type -Sequential / Interleave (program-
mable)
Auto precharge/ All bank precharge controlled
by A10
8192 refresh cycles / 64ms (4 banks concurrent
refresh)
Auto refresh and Self refresh
Row address A0-12 / Column address A0-8(x16)
SSTL_2 Interface
Package 400-mil, 66-pin Thin Small Outline
Package (TSOP II) with 0.65mm lead pitch
Temperature Range:
Commercial (0
dd
=V
ddq
= 2.5V+0.2V (-5, -6, -75)
o
C to +70
16M x 16
4M x 16 x 4 banks
BA0, BA1
A10/AP
A0 – A12
A0 – A8
8192 / 64ms
o
C)
DESCRIPTION:
IS43R16160 is a 4-bank x 4,194,304-word x 16bit
double data rate synchronous DRAM , with SSTL_2
interface. All control and address signals are referenced
to the rising edge of CLK. Input data is registered on
both edges of data strobe, and output data and data
strobe are referenced on both edges of CLK. The device
achieves very high speed clock rate up to 200 MHz.
KEY TIMING PARAMETERS
Parameter
Clk Cycle Time
Clk Frequency
Access Time from Clock
CAS Latency = 3
CAS Latency = 2.5
CAS Latency = 2
CAS Latency = 3
CAS Latency = 2.5
CAS Latency = 2
CAS Latency = 3
CAS Latency = 2.5
CAS Latency = 2
PRELIMINARY INFORMATION
OCTOBER 2008
+0.70 +0.70 +0.75
+0.70 +0.70 +0.75
+0.75 +0.75 +0.75
200
200
143
7.5
-5
5
5
167
167
143
7.5
-6
6
6
143
143
143
-75
7.5
7.5
7.5
MHz
MHz
MHz
Unit
ns
ns
ns
ns
ns
ns
1

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