LTC1743 Linear Technology, LTC1743 Datasheet

no-image

LTC1743

Manufacturer Part Number
LTC1743
Description
12-Bit 50Msps ADC
Manufacturer
Linear Technology
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
LTC1743CFW#PBF
Manufacturer:
LINEAR/凌特
Quantity:
20 000
Part Number:
LTC1743IFW#TRPBF
Manufacturer:
LINEAR/凌特
Quantity:
20 000
FEATURES
BLOCK DIAGRA
APPLICATIO S
, LTC and LT are registered trademarks of Linear Technology Corporation.
Sample Rate: 50Msps
72.5dB SNR and 85dB SFDR (3.2V Range)
71dB SNR and 90dB SFDR (2V Range)
No Missing Codes
Single 5V Supply
Power Dissipation: 1000mW
Selectable Input Ranges: 1V or 1.6V
150MHz Full Power Bandwidth S/H
Pin Compatible Family
25Msps: LTC1746 (14-Bit), LTC1745 (12-Bit)
50Msps: LTC1744 (14-Bit), LTC1743 (12-Bit)
65Msps: LTC1742 (14-Bit), LTC1741 (12-Bit)
80Msps: LTC1748 (14-Bit), LTC1747 (12-Bit)
48-Pin TSSOP Package
Telecommunications
Receivers
Cellular Base Stations
Spectrum Analysis
Imaging Systems
ANALOG INPUT
DIFFERENTIAL
4.7 F
1V
SENSE
A
A
V
IN
IN
CM
+
U
2.5V
SELECT
RANGE
REF
W
BUFFER
50Msps, 12-Bit ADC with a 2V Differential Input Range
AMP
S/H
DIFF AMP
0.1 F
REFLB
1 F
PIPELINED ADC
12-BIT
REFHA
4.7 F
DESCRIPTIO
The LTC
verter designed for digitizing high frequency, wide
dynamic range signals. Pin selectable input ranges of 1V
and 1.6V along with a resistor programmable mode
allow the LTC1743’s input range to be optimized for a
wide variety of applications.
The LTC1743 is perfect for demanding communications
applications with AC performance that includes 72.5dB
SNR and 85dB spurious free dynamic range. Ultralow jitter
of 0.3ps
excellent noise performance. DC specs include 1LSB
maximum INL and 0.8LSB DNL over temperature.
The digital interface is compatible with 5V, 3V and 2V logic
systems. The ENC and ENC inputs may be driven differen-
tially from PECL, GTL and other low swing logic families or
from single-ended TTL or CMOS. The low noise, high gain
ENC and ENC inputs may also be driven by a sinusoidal
signal without degrading performance. A separate output
power supply can be operated from 0.5V to 5V, making it
easy to connect directly to any low voltage DSPs or FIFOs.
The 48-pin TSSOP package with a flow-through pinout
simplifies the board layout.
REFLA
1 F
0.1 F
RMS
®
REFHB
1743 is a 50Msps, sampling 12-bit A/D con-
ENCODE INPUT
DIFFERENTIAL
allows undersampling of IF frequencies with
ENC
CONTROL LOGIC
ENC
U
12-Bit, 50Msps ADC
12
MSBINV
LATCHES
OUTPUT
OE
GND
1743 BD
OV
OGND
V
DD
www.DataSheet4U.com
DD
OF
D11
D0
CLKOUT
0.1 F
1 F
1 F
LTC1743
0.1 F
0.5V TO 5V
1 F
5V
1
1743f

Related parts for LTC1743

LTC1743 Summary of contents

Page 1

... Pin selectable input ranges of 1V and 1.6V along with a resistor programmable mode allow the LTC1743’s input range to be optimized for a wide variety of applications. The LTC1743 is perfect for demanding communications applications with AC performance that includes 72.5dB SNR and 85dB spurious free dynamic range ...

Page 2

... Digital Output Voltage ................. – 0. OGND Voltage ..............................................– 0. Power Dissipation ............................................ 2000mW Operating Temperature Range LTC1743C ............................................... LTC1743I ............................................ – Storage Temperature Range ................. – 150 C Lead Temperature (Soldering, 10 sec).................. 300 VERTER CHARACTERISTICS temperature range, otherwise specifications are at T ...

Page 3

... IN2 f = 2.52MHz 5.2MHz (3.2V Range) IN1 IN2 SOURCE (Note 5) CONDITIONS OUT OUT 4.75V V 5.25V DD 1mA I 1mA OUT LTC1743 MIN TYP MAX UNITS 71 dBFS 70 72.5 dBFS 70.5 dBFS 72.0 dBFS 68.5 dBFS 69.5 dBFS ...

Page 4

... LTC1743 U U DIGITAL I PUTS A D DIGITAL OUTPUTS operating temperature range, otherwise specifications are at T SYMBOL PARAMETER V High Level Input Voltage IH V Low Level Input Voltage IL I Digital Input Current IN C Digital Input Capacitance IN V High Level Output Voltage OH V Low Level Output Voltage ...

Page 5

... FREQUENCY (MHz) 1743 G08 LTC1743 www.DataSheet4U.com Nonaveraged, 8192 Point FFT, Input Frequency = 2.5MHz, –1dB 2V Range 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 0 ...

Page 6

... LTC1743 W U TYPICAL PERFOR A CE CHARACTERISTICS Averaged, 8192 Point FFT, Input Frequency = 2.5MHz, –6dB, 3.2V Range 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 FREQUENCY (MHz) 1743 G10 Averaged, 8192 Point FFT, Input Frequency = 20MHz, –6dB, 2V Range 0 – ...

Page 7

... G23 SNR vs Input Frequency and Amplitude, 3.2V Range 75 –1dBFS 70 –6dBFS –20dBFS 100 INPUT FREQUENCY (MHz) 1743 G26 LTC1743 www.DataSheet4U.com Averaged, 8192 Point FFT, Input Frequency = 70MHz, –6dB, 2V Range 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 – ...

Page 8

... LTC1743 W U TYPICAL PERFOR A CE CHARACTERISTICS SFDR vs Input Frequency and Amplitude, 3.2V Range 110 100 –20dBFS 90 –6dBFS 80 –1dBFS 100 INPUT FREQUENCY (MHz) 1743 G28 2nd and 3rd Harmonic vs Input Frequency, 2V Range, –1dB –60 –70 3RD HARMONIC –80 –90 –100 2ND HARMONIC – ...

Page 9

... Positive Supply for the Output Driv- DD ers. Bypass to ground with 0.1 F ceramic chip capacitor. D2-D4 (Pins 33 to 35): Digital Outputs. D5-D8 (Pins 39 to 42): Digital Outputs. D9-D11 (Pins 44 to 46): Digital Outputs. D11 is the MSB. OF (Pin 48): Over/Under Flow Output. High when an over or under flow has occurred. LTC1743 1743f 9 ...

Page 10

... LTC1743 DIAGRA N ANALOG INPUT t 3 ENCODE t 6 DATA t 5 CLKOUT DATA CTIO AL BLOCK DIAGRA + DIFFERENTIAL ANALOG INPUT – SENSE BUFFER RANGE SELECT V CM 2.5V REF 4 DATA (N – 5) D11 DATA N ...

Page 11

... DC. This value is expressed in decibels relative to the RMS value of a full scale input signal Input Bandwidth The input bandwidth is that input frequency at which the amplitude of the reconstructed fundamental is reduced by 3dB for a full scale input signal. LTC1743 www.DataSheet4U.com 1743f 11 ...

Page 12

... T JITTER IN CONVERTER OPERATION As shown in Figure 1, the LTC1743 is a CMOS pipelined multistep converter. The converter has four pipelined ADC stages; a sampled analog input will result in a digitized value five cycles later, see the Timing Diagram section. The analog input is differential for improved common ...

Page 13

... SAMPLE/HOLD OPERATION AND INPUT DRIVE Sample Hold Operation Figure 2 shows an equivalent circuit for the LTC1743 CMOS differential sample-and-hold. The differential ana- log inputs are sampled directly onto sampling capacitors (C ) through CMOS transmission gates ...

Page 14

... Poor matching will result in higher even order harmonics, especially the second. Input Drive Circuits output pin CM Figure 3 shows the LTC1743 being driven transformer with a center tapped secondary. The second- ary center tap is DC biased with V signal at its optimum DC level. Figure 3 shows a 1:1 turns pin must be CM ratio transformer ...

Page 15

... A IN Reference Operation 37 18pF Figure 5 shows the LTC1743 reference circuitry consisting 1743 F04a of a 2.5V bandgap reference, a difference amplifier and switching and control circuit. The internal voltage refer- ence can be configured for two pin selectable input ranges of 2V( 1V differential) or 3.2V( 1.6V differential). Tying the SENSE pin to ground selects the 2V range ...

Page 16

... SNR will degrade by 1.5dB. See the Typical Performance Characteristics section. Driving the Encode Inputs The noise performance of the LTC1743 can depend on the encode signal quality as much as on the analog input. The ENC/ENC inputs are intended to be driven differentially, primarily for noise immunity from common mode noise sources ...

Page 17

... Each input may be driven from ground single-ended drive. LTC1743 5V 2V BIAS ENC 1:4 2V BIAS ENC MC100LVELT22 LTC1743 1743 F08a Figure 8b. ENC Drive Using a CMOS-to-PECL Translator LTC1743 www.DataSheet4U.com DD BIAS TO INTERNAL ADC CIRCUITS 1743 F07 3.3V 3.3V 130 130 Q0 ENC D0 LTC1743 ENC 1743 F08b 17 for 1743f ...

Page 18

... At sample rates slower than 50Msps the duty cycle can vary from 50% as long as each half cycle is at least 9.5ns. The lower limit of the LTC1743 sample rate is determined by the droop of the sample-and-hold circuits. The pipelined architecture of this ADC relies on storing analog signals on small valued capacitors ...

Page 19

... ADC OGND (Pin 38). HEAT TRANSFER Most of the heat generated by the LTC1743 is transferred from the die through the package leads onto the printed circuit board. In particular, ground pins 12, 13, 36 and 37 are fused to the die attach pad. These pins have the lowest thermal resistance between the die and the outside envi- ronment ...

Page 20

... LTC1743 U U APPLICATIO S I FOR ATIO www.DataSheet4U.com 1743f ...

Page 21

... U U APPLICATIO S I FOR ATIO W U Topside Silkscreen Topside Copper Layer Ground Plane, Layer 2 LTC1743 www.DataSheet4U.com 1743f 21 ...

Page 22

... LTC1743 U U APPLICATIO S I FOR ATIO Split Power Plane, Layer 3 Bottom Side Copper, Layer 1743f ...

Page 23

... BSC LTC1743 www.DataSheet4U.com 7.9 – 8.3 (.311 – .327) 1.20 (.0473) MAX -T- .10 C FW48 TSSOP 0502 0.05 – ...

Page 24

... Accuracy, 10ppm/ C Drift 16-Bit, No Missing Codes, 90dB SINAD, –100dB THD 87dB SFDR at 1MHz f Pin Compatible with LTC1743 Pin Compatible with LTC1743 77dB SNR, Pin Compatible with LTC1743 Pin Compatible with LTC1743 Pin Compatible with LTC1743 Pin Compatible with LTC1743 Pin Compatible with LTC1743 www ...

Related keywords