mc10e1651 ON Semiconductor, mc10e1651 Datasheet

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mc10e1651

Manufacturer Part Number
mc10e1651
Description
5 V, -5 V Dual Ecl Output Comparator With Latch
Manufacturer
ON Semiconductor
Datasheet

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MC10E1651
5V, -5V Dual ECL Output
Comparator with Latch
advanced MOSAIC III™ process. The MC10E1651 incorporates a
fixed level of input hysteresis as well as output compatibility with 10
KH logic devices. In addition, a latch is available allowing a sample
and hold function to be performed. The device is available in both a
16‐pin DIP and a 20‐pin surface mount package.
ECL 10 KH logic levels. When the latch enable is at a logic high level,
the MC10E1651 acts as a comparator; hence, Q will be at a logic high
level if V1 > V2 (V1 is more positive than V2). Q is the complement
of Q. When the latch enable input goes to a low logic level, the outputs
are latched in their present state providing the latch enable setup and
hold time constraints are met.
Features
*For additional information on our Pb-Free strategy and soldering details, please
© Semiconductor Components Industries, LLC, 2007
August, 2007 - Rev. 9
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
The MC10E1651 is fabricated using ON Semiconductor's
The latch enable (LEN
> 100 V Machine Model
For Additional Information, see Application Note AND8003/D
Oxygen Index: 28 to 34
Typical 3.0 dB Bandwidth > 1.0 GHz
Typical V to Q Propagation Delay of 775 ps
Typical Output Rise/Fall of 350 ps
Common Mode Range -2.0 V to +3.0 V
Individual Latch Enables
Differential Outputs
28 mV Input Hysteresis
Operating Mode: V
No Internal Input Pulldown Resistors
ESD Protection: > 2 kV Human Body Model,
Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
Moisture Sensitivity Level 1
Flammability Rating: UL 94 V-0 @ 0.125 in,
Transistor Count = 85 devices
Pb-Free Packages are Available*
CC
a
= 5.0 V, V
and LEN
b
EE
) input pins operate from standard
= -5.2 V, GND = 0 V
1
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
20 1
CASE 620A
FN SUFFIX
CASE 775
L SUFFIX
PLCC-20
CDIP-16
ORDERING INFORMATION
A
WL
YY
WW
G
http://onsemi.com
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb-Free Package
Publication Order Number:
16
1
DIAGRAMS
MC10E1651L
AWLYYWW
MARKING
AWLYYWW
MC10E1651/D
1651FNG
MC10E
1 20

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mc10e1651 Summary of contents

Page 1

... ECL 10 KH logic levels. When the latch enable logic high level, the MC10E1651 acts as a comparator; hence, Q will logic high level if V1 > V2 (V1 is more positive than V2 the complement of Q. When the latch enable input goes to a low logic level, the outputs are latched in their present state providing the latch enable setup and hold time constraints are met ...

Page 2

... Qb, Qb ECL Differential Outputs (b) LENa, LENb ECL Latch Enable V1a, V1b Input Comparator 1 V2a, V2b Input Comparator 2 V Positive Supply CC V Negative Supply Connect GND Ground MC10E1651 14 GND 16‐Pin Ceramic DIP (Top View ...

Page 3

... Hence the skew hysteresis window ranged from 14 mV below the reference level above the reference level. All hysteresis measurements were determined using a reference voltage of 0 mV. MC10E1651 Condition ...

Page 4

... Refer to Figure 5 and note that the input is at 2.5 V TTL levels with the input threshold range between the 20% and 80% points. The delay is measured from the crosspoint of the input signal and the threshold value to the crosspoint of the Q and Q output signals. 10. The slew rate is 0.3 V/NS for input rising edges. MC10E1651 = +5.0 V ±5 -5.2 V ±5%, GND = 0 V (Note 4) ...

Page 5

... The timing diagram (Figure 3.) is presented to illustrate the MC10E1651's compare and latch features. When the signal on the LEN pin logic high level, the device is operating in the “compare mode,” and the signal on the input arrives at the output after a nominal propagation delay ( ...

Page 6

... SLEW RATE = 0.25 V/NS INPUT THRESHOLD SLEW RATE = 0.75 V/NS RANGE - 1. 1.75 V Figure 4. ECL Dispersion Test Input Conditions MC10E1651 DELAY DISPERSION where T NOM accounts for nonuniformity introduced by temperature and voltage variability, whereas the delay dispersion parameter and takes into consideration input slew rate and input voltage DE overdrive variability ...

Page 7

... Application Note AND8020/D - Termination of ECL Logic Devices.) ORDERING INFORMATION Device MC10E1651L MC10E1651FN MC10E1651FNG MC10E1651FNR2 MC10E1651FNR2G †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Resource Reference of Application Notes AN1405/D AN1406/D AN1503/D ...

Page 8

... 0.25 (0.010) MC10E1651 PACKAGE DIMENSIONS CDIP-16 L SUFFIX CERAMIC DIP PACKAGE CASE 620A-01 ISSUE 16X 0.25 (0.010 SEATING T PLANE D 16X http://onsemi.com 8 NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL ...

Page 9

... DIMENSION H DOES NOT INCLUDE DAMBAR PROTRUSION OR INTRUSION. THE DAMBAR PROTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE GREATER THAN 0.037 (0.940). THE DAMBAR INTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE SMALLER THAN 0.025 (0.635). MC10E1651 PACKAGE DIMENSIONS 20 LEAD PLLC CASE 775-02 ISSUE E 0.007 (0.180) ...

Page 10

... N. American Technical Support: 800-282-9855 Toll Free  USA/Canada Europe, Middle East and Africa Technical Support:  Phone: 421 33 790 2910 Japan Customer Focus Center  Phone: 81-3-5773-3850 http://onsemi.com 10 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative MC10E1651/D ...

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