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DataSheet
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Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î
4
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
1-to-64 Bit Variable Length
Shift Register
be programmed to be any number of bits between 1 and 64. The number of
bits selected is equal to the sum of the subscripts of the enabled Length
Control inputs (L1, L2, L4, L8, L16, and L32) plus one. Serial data may be
selected from the A or B data inputs with the A/B select input. This feature is
useful for recirculation purposes. A Clock Enable (CE) input is provided to
allow gating of the clock or negative edge clocking capability.
to implement odd length shift registers.
* Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:
REV 3
1/94
U
MAXIMUM RATINGS*
V in , V out
Symbol
MOTOROLA CMOS LOGIC DATA
I in , I out
.com
The MC14557B is a static clocked serial shift register whose length may
The device can be effectively used for variable digital delay lines or simply
Motorola, Inc. 1995
V DD
1–64 Bit Programmable Length
Q and Q Serial Buffered Outputs
Asynchronous Master Reset
All Inputs Buffered
No Limit On Clock Rise and Fall Times
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Capable of Driving Two Low–power TTL Loads or one Low–power
Schottky TTL Load Over the Rated Temperature Range
T stg
P D
T L
Plastic “P and D/DW” Packages: – 7.0 mW/
Ceramic “L” Packages: – 12 mW/
NOTE: Length equals the sum of the binary length control
L32
DC Supply Voltage
Input or Output Voltage (DC or Transient)
Input or Output Current (DC or Transient),
per Pin
Power Dissipation, per Package†
Storage Temperature
Lead Temperature (8–Second Soldering)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
subscripts plus one.
L16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
LENGTH SELECT TRUTH TABLE
L8
(Voltages Referenced to V SS )
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Parameter
L4
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
_
C From 100
L2
0
0
0
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
L1
0
1
1
0
0
0
1
1
1
1
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
_
C From 65
_
C To 125
Register Length
– 0.5 to V DD + 0.5
33 Bits
33 Bits
33 Bits
33 Bits
33 Bits
33 Bits
33 Bits
33 Bits
33 Bits
33 Bits
33 Bits
33 Bits
33 Bits
33 Bits
34 Bits
34 Bits
34 Bits
34 Bits
34 Bits
34 Bits
34 Bits
34 Bits
34 Bits
34 Bits
34 Bits
34 Bits
34 Bits
34 Bits
61 Bits
61 Bits
61 Bits
61 Bits
61 Bits
61 Bits
61 Bits
61 Bits
61 Bits
61 Bits
61 Bits
61 Bits
61 Bits
61 Bits
62 Bits
62 Bits
62 Bits
62 Bits
62 Bits
62 Bits
62 Bits
62 Bits
62 Bits
62 Bits
62 Bits
62 Bits
62 Bits
62 Bits
63 Bits
63 Bits
63 Bits
63 Bits
63 Bits
63 Bits
63 Bits
63 Bits
63 Bits
63 Bits
63 Bits
63 Bits
63 Bits
63 Bits
64 Bits
64 Bits
64 Bits
64 Bits
64 Bits
64 Bits
64 Bits
64 Bits
64 Bits
64 Bits
64 Bits
64 Bits
64 Bits
64 Bits
– 0.5 to + 18.0
2 Bits
2 Bits
3 Bits
3 Bits
3 Bits
4 Bits
4 Bits
4 Bits
4 Bits
5 Bits
5 Bits
5 Bits
5 Bits
5 Bits
6 Bits
6 Bits
6 Bits
6 Bits
6 Bits
6 Bits
_
– 65 to + 150
1 Bit
C To 125
_
C
Value
500
260
10
_
C
Unit
mW
mA
_
_
V
V
C
C
Q is the output of the first selected shift
X = Don’t Care
register stage.
Rst
T A = – 55 to 125 C for all packages.
0
0
0
0
1
15
14
13
12
3
4
5
6
7
9
2
1
ORDERING INFORMATION
MC14XXXBCP
MC14XXXBCL
MC14XXXBDW
MC14557B
A/B
BLOCK DIAGRAM
X
0
1
0
1
Inputs
RESET
CLOCK
CE
B
A
A/B SELECT
L1
L2
L4
L8
L16
L32
TRUTH TABLE
V DD = PIN 16
V SS = PIN 8
Clock
X
1
1
DW SUFFIX
CASE 751G
CE
CERAMIC
CASE 620
CASE 648
0
0
X
L SUFFIX
P SUFFIX
PLASTIC
Q
Q
Plastic
Ceramic
SOIC
SOIC
MC14557B
Output
Q
B
A
B
A
10
11
0
1