MC68LK332 Motorola, MC68LK332 Datasheet

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MC68LK332

Manufacturer Part Number
MC68LK332
Description
MC68LK332Technical Supplement 16.78 MHz Electrical Characteristics
Manufacturer
Motorola
Datasheet

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© MOTOROLA INC, 1997
Technical Supplement
16.78 MHz Electrical Characteristics
MOTOROLA
SEMICONDUCTOR
TECHNICAL DATA
Devices in the 68300 Modular Microcontroller Family are built up from a selection of standard functional
modules. The MC68LK332 incorporates a central processing unit (CPU32), a system integration
module (SIM), a queued serial module (QSM), a time processor unit (TPU), and a 2 K-byte static RAM
module with TPU emulation capability (TPURAM). The functionality of the MC68LK332 is enhanced
from the MC68L332 to include an operational PLL.
This publication contains a new electrical characteristics appendix for the MC68LK332 to be used in
conjunction with the MC68332 User's Manual (MC68332UM/AD).
PRELIMINARY
MC68LK332
Order this document by
MC68LK332EC16/D

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MC68LK332 Summary of contents

Page 1

... K-byte static RAM module with TPU emulation capability (TPURAM). The functionality of the MC68LK332 is enhanced from the MC68L332 to include an operational PLL. This publication contains a new electrical characteristics appendix for the MC68LK332 to be used in conjunction with the MC68332 User's Manual (MC68332UM/AD). PRELIMINARY © ...

Page 2

... BDM Freeze Assertion Timing Diagram ....................................................................................21 15 ECLK Timing Diagram ...............................................................................................................23 16 QSPI Timing — Master, CPHA = 0 ...........................................................................................25 17 QSPI Timing — Master, CPHA = 1 ...........................................................................................25 18 QSPI Timing — Slave, CPHA = 0 .............................................................................................26 19 QSPI Timing — Slave, CPHA = 1 .............................................................................................26 20 TPU Timing Diagram .................................................................................................................27 MOTOROLA 2 LIST OF ILLUSTRATIONS Title Page MC68LK332 MC68LK332EC16/D ...

Page 3

... Table 1 Maximum Ratings ........................................................................................................................4 2 MC68LK332 Typical Ratings .......................................................................................................5 3 Thermal Characteristics ..............................................................................................................5 4 Clock Control Timing ...................................................................................................................6 5 16.78 MHz DC Characteristics ....................................................................................................7 6 16.78 MHz AC Timing .................................................................................................................9 7 Background Debugging Mode Timing .......................................................................................21 8 ECLK Bus Timing ......................................................................................................................22 9 QSPI Timing ..............................................................................................................................24 10 Time Processor Unit Timing ......................................................................................................27 MC68LK332 MC68LK332EC16/D LIST OF TABLES ...

Page 4

... 0 stg Value Unit – 0 6.5 V – – 500 to 500 – – 150 C range during instantaneous and . All functional pins except EXTAL MC68LK332 MC68LK332EC16/D ...

Page 5

... Table 2 MC68LK332 Typical Ratings Num Rating 1 Supply Voltage 2 Operating Temperature V Supply Current DD RUN 3 LPSTOP, VCO off LPSTOP, External clock, max f 4 Clock Synthesizer Operating Voltage V Supply Current DDSYN VCO on, maximum f sys 5 External Clock, maximum f LPSTOP, VCO off V powered down DD RAM Standby Current ...

Page 6

... X must equal one when operating at maximum sys VCO and V DDSYN = Min Max Unit 20 50 kHz ) 16.78 MHz ref dc 16.78 — — max) MHz sys 1.0 % 0.5 to guarantee this . = f sys VCO and variation in crystal oscillator SS MC68LK332 MC68LK332EC16/D ...

Page 7

... Supply Current DDSYN External clock, maximum f sys 14 Crystal reference, VCO on, maximum f LPSTOP, crystal reference, VCO off, (STSIM = 0) V powered down DD RAM Standby Voltage Specified V applied MC68LK332 MC68CK331EC16/D = 3.0 to 3.6 Vdc Vdc Symbol HYS ...

Page 8

... — — — 212 — — 20 — — 100 pF L — 100 — 100 supply current. DDSYN and V pins, which causes STBY DD and V DD STBY does not exceed V by more than 0.5 DD MC68LK332 MC68LK332EC16/D ...

Page 9

... Clock High to AS, DS, R/W High Impedance 17 AS, DS, CS Negated to R/W High 18 Clock High to R/W High 20 Clock High to R/W Low 21 R/W High to AS, CS Asserted 22 R/W Low to DS, CS Asserted (Write) 23 Clock High to Data Out Valid MC68LK332 MC68CK331EC16/D Table 6 16.78 MHz AC Timing = 3.0 to 3.6 Vdc Vdc Symbol ...

Page 10

... AIST t 15 — ns AIHT t — DABA t 0 — ns DOCH t — CHDH t 40 — ns RADC SCLDD t 15 — ns SCLDS t 10 — ns SCLDH t 15 — ns BKST t 10 — ns BKHT t 20 — t MSS cyc t 0 — ns MSH MC68LK332 MC68LK332EC16/D ...

Page 11

... External assertion of the RESET input can overlap internally-generated resets. To insure that an external reset is recognized in all cases, RESET must be asserted for at least 590 CLKOUT cycles. 12. External logic must pull RESET high during this period in order for normal MCU operation to begin. MC68LK332 MC68CK331EC16/D = 3.0 to 3.6 Vdc, V ...

Page 12

... EXTAL NOTE: PULSE WIDTH SHOWN WITH RESPECT TO 50% V Figure 2 External Clock Input Timing Diagram 4A ECLK Figure 3 ECLK Output Timing Diagram MOTOROLA 68300 CLKOUT TIM 3B 68300 EXT CLK INPUT TIM 68300 ECLK OUTPUT TIM MC68LK332 MC68LK332EC16/D ...

Page 13

... CLKOUT ADDR[23:20] FC[2:0] SIZ[1: R/W DSACK0 DSACK1 DATA[15:0] BERR HALT IFETCH BKPT ASYNCHRONOUS INPUTS Figure 4 Read Cycle Timing Diagram MC68LK332 MC68CK331EC16 47A 31 27 29A 48 27A 9C 12A 73 47A 47B 12A 74 68300 RD CYC TIM ...

Page 14

... CLKOUT 6 ADDR[23:20] FC[2:0] SIZ[1: R/W DSACK0 DSACK1 DATA[15:0] BERR HALT BKPT Figure 5 Write Cycle Timing Diagram MOTOROLA 14A 46 47A 27A 68300 WR CYC TIM MC68LK332 MC68LK332EC16/D ...

Page 15

... CLKOUT ADDR[23:0] FC[2:0] SIZ[1: R/W DATA[15:0] BKPT Figure 6 Fast Termination Read Cycle Timing Diagram MC68LK332 MC68CK331EC16 14B 46A 27 30 30A 29A 68300 FAST RD CYC TIM MOTOROLA 15 ...

Page 16

... CLKOUT ADDR[23:0] FC[2:0] SIZ[1:0] DATA[15:0] BKPT Figure 7 Fast Termination Write Cycle Timing Diagram MOTOROLA 14B 46A 20 R 68300 FAST WR CYC TIM MC68LK332 MC68LK332EC16/D ...

Page 17

... S0 S1 CLKOUT ADDR[23:0] DATA[15: R/W DSACK0 DSACK1 BR BG BGACK Figure 8 Bus Arbitration Timing Diagram — Active Bus Case MC68LK332 MC68CK331EC16 S98 47A 39A 33 37 68300 BUS ARB TIM MOTOROLA 17 ...

Page 18

... A0 CLKOUT ADDR[23:0] DATA[15:0] AS 47A BGACK Figure 9 Bus Arbitration Timing Diagram — Idle Bus Case MOTOROLA 47A 47A 68300 BUS ARB TIM IDLE MC68LK332 MC68LK332EC16/D ...

Page 19

... CLKOUT ADDR[23:0] R DATA[15:0] BKPT NOTE: SHOW CYCLES CAN STRETCH DURING CLOCK PHASE S42 WHEN BUS ACCESSES TAKE LONGER THAN TWO CYCLES DUE TO IMB MODULE WAIT-STATE INSERTION. Figure 10 Show Cycle Timing Diagram MC68LK332 MC68CK331EC16/D S0 S41 S42 S43 ...

Page 20

... Figure 11 Chip-Select Timing Diagram 77 RESET DATA[15:0] Figure 12 Reset and Mode Select Timing Diagram MOTOROLA 29A 14A 68300 CHIP SEL TIM 68300 RST/MODE SEL TIM MC68LK332 MC68LK332EC16/D ...

Page 21

... B9 DSCLK Low Time NOTES: 1. All AC timing is shown with respect to 20% V CLKOUT FREEZE BKPT/DSCLK IFETCH/DSI IPIPE/DSO Figure 13 BDM Serial Communication Timing Diagram CLKOUT FREEZE IFETCH/DSI Figure 14 BDM Freeze Assertion Timing Diagram MC68LK332 MC68CK331EC16/D = 3.0 to 3.6 Vdc Vdc Symbol t DSISU t DSIH t DSCSU t DSCH ...

Page 22

... ECSD t 15 — ns ECSH t 30 — ns ECSN t 30 — ns EDSR t 5 — ns EDHR t — EDHZ t 0 — ns ECDH t — ECDZ cyc t — EDDW cyc t 15 — ns EDHW t 386 — ns EACC t 296 — ns EACS t 1/2 — t EAS cyc MC68LK332 MC68LK332EC16/D ...

Page 23

... CLKOUT 2A ECLK R/W E1 ADDR[23: E15 DATA[15:0] E11 DATA[15:0] MC68LK332 MC68CK331EC16 E14 E13 WRITE Figure 15 ECLK Timing Diagram READ WRITE E7 E8 E10 E12 68300 E CYCLE TIM MOTOROLA 23 ...

Page 24

... V levels unless otherwise noted Unit f sys f sys t cyc t cyc t cyc t cyc SCK t cyc cyc t cyc cyc t cyc MC68LK332 MC68LK332EC16/D ...

Page 25

... Figure 16 QSPI Timing — Master, CPHA = 0 PCS[3:0] OUTPUT SCK CPOL=0 OUTPUT SCK CPOL=1 OUTPUT MISO MSB IN INPUT MOSI PORT DATA OUTPUT 13 Figure 17 QSPI Timing — Master, CPHA = 1 MC68LK332 MC68CK331EC16 DATA LSB DATA LSB OUT PORT DATA ...

Page 26

... DATA LSB OUT DATA LSB SLAVE MSB OUT DATA LSB OUT MSB IN DATA LSB MSB OUT MSB IN 68300 QSPI SLV CPHA0 68300 QSPI SLV CPHA1 MC68LK332 MC68LK332EC16/D ...

Page 27

... AC Timing is shown with respect to 20 Timing not valid for external T2CLK input. 3. Maximum load capacitance for CLKOUT pin is 90 pF. 4. Maximum load capacitance for TPU output pins is 100 pF. CLKOUT 1 TPU OUTPUT TPU INPUT MC68LK332 MC68CK331EC16/D = 3.0 to 3.6Vdc Vdc, T DDA SS Symbol ...

Page 28

... Mfax™: RMFAX0@email.sps.mot.com - TOUCHTONE (602) 244-6609, U.S. and Canada Only 1-800-774-1848 INTERNET: http://motorola.com/sps JAPAN: Nippon Motorola Ltd.,Strategic Planning Office, 4-32-1, Nishi-Gotanda, Shinagawa-ku, Tokyo 141, Japan. 81-3-5487-8488 ASIA PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852-26629298 Mfax is a trademark of Motorola, Inc. MC68LK332EC16/D ...

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