MPC9352 Motorola, MPC9352 Datasheet
MPC9352
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MPC9352 Summary of contents
Page 1
... FSELx pins supporting systems with different but phase-aligned clock frequencies. The PLL of the MPC9352 minimizes the propagation delay and therefore supports zero-delay applications. All inputs and outputs are LVCMOS compatible. The outputs are optimized to drive parallel terminated 50Ω transmission lines. Alternatively, each output can drive up to two series terminated transmission lines giving the device an effective fanout of 22 ...
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... Freescale Semiconductor, Inc. MPC9352 PLL Figure 2. MPC9352 32–Lead Package Pinout (Top View) MOTOROLA For More Information On This Product, ÷2 ÷ ÷4 ÷2 W Figure 1. MPC9352 Logic Diagram MPC9352 2 Go to: www.freescale.com TIMING SOLUTIONS ...
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... Outputs disabled (high–impedance state) and reset of the device. During reset, the PLL feedback loop is open and the VCO is operating at its lowest frequency. The MPC9352 requires reset at power–up and after any loss of PLL lock. Loss of PLL lock may occur when the external feedback path is interrupted ...
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... CCA I c Maximum Quiescent Supply Current CCQ a The MPC9352 is capable of driving 50Ω transmission lines on the incident edge. Each output drives one 50Ω parallel terminated transmission line to a termination voltage Inputs have pull-down resistors affecting the input current the DC current consumption of the device with all outputs open in high impedance state and the inputs in its default state or open. ...
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... PLL mode requires PLL_EN=0 to enable the PLL and zero-delay operation not recommended to use a ÷2 divider for feedback PLL bypass mode, the MPC9352 divides the input reference clock. d The input frequency f on CCLK must match the VCO frequency range divided by the feedback divider ratio FB: f ...
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... I b Maximum Quiescent Supply Current CCQ a The MPC9352 is capable of driving 50Ω transmission lines on the incident edge. Each output drives one 50Ω parallel terminated transmission line to a termination voltage of V output the DC current consumption of the device with all outputs open in high impedance state and the inputs in its default state or open. ...
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... PLL mode requires PLL_EN=0 to enable the PLL and zero-delay operation not recommended to use a ÷2 divider for feedback PLL bypass mode, the MPC9352 divides the input reference clock. d The input frequency f on CCLK must match the VCO frequency range divided by the feedback divider ratio FB: f ...
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... Possible frequency ratios of the reference clock input to the outputs are 1:1, 1:2, 1:3, 3:2 as well as 2:3, 3:1 and 2:1. Table 1 illustrates the various output configurations and frequency ratios supported by the MPC9352. See also Table 9, Table 10 and Figure 3 to Figure 6 for further reference. A feedback. FSELB ...
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... MHz TIMING SOLUTIONS For More Information On This Product, Figure 4. MPC9352 Zero Delay Buffer Configuration MPC9352 zero–delay (feedback of QB0 = 62.5 MHz). All control pins are left open except FSELC = 1. All outputs are locked in frequency and phase to the input clock. Max Frequency range ...
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... CMOS fanout buffers. The external feedback option of the MPC9352 clock driver allows for its use as a zero delay buffer. One example configuration is to use a ÷4 output as a feedback to the PLL and configuring all other outputs to a divide-by-4 mode ...
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... This suggests that the dual line driving need not be used exclusively to maintain the tight output-to-output skew of the MPC9352. The output waveform in Figure 11. “Single versus Dual Line Termination Waveforms” shows a step in the waveform, this step is caused by the impedance mismatch seen looking into the driver. The parallel combination of the 36Ω ...
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... Since this step is well above the threshold region it will not cause any false clock triggering, however designers may be uncomfortable with unwanted reflections on the line. To better W Figure 13. CCLK MPC9352 AC test reference for V MOTOROLA For More Information On This Product, match the impedances when driving multiple lines the situation in Figure 12. “ ...
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... Figure 18. Cycle–to–cycle Jitter Figure 20. Output Transition Time Test Reference TIMING SOLUTIONS For More Information On This Product ∅ Figure 15. Propagation delay (t SK( N to: www.freescale.com MPC9352 static phase (∅) offset) test reference mean JIT(∅ Figure 17. I/O Jitter T ...
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... Freescale Semiconductor, Inc. MPC9352 –T– DETAIL –Z– –AB– SEATING –AC– PLANE DETAIL AD MOTOROLA For More Information On This Product, OUTLINE DIMENSIONS FA SUFFIX LQFP PACKAGE CASE 873A-02 ISSUE A 4X – ...
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... Freescale Semiconductor, Inc. TIMING SOLUTIONS For More Information On This Product, NOTES 15 Go to: www.freescale.com MPC9352 MOTOROLA ...
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... JAPAN: Motorola Japan Ltd.; SPS, Technical Information Center, 3–20–1, Minami–Azabu, Minato–ku, Tokyo 106–8573, Japan 81–3–3440–3569 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre, 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong 852–26668334 HOME PAGE: http://motorola.com/semiconductors 16 Go to: www.freescale.com MPC9352/D TIMING SOLUTIONS ...