SSTU32864 Philips Semiconductors, SSTU32864 Datasheet

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SSTU32864

Manufacturer Part Number
SSTU32864
Description
1.8V confgurable registered buffer
Manufacturer
Philips Semiconductors
Datasheet

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1. Description
The SSTU32864 is a 25-bit 1:1 or 14-bit 1:2 configurable registered buffer designed
for 1.7 V to 1.9 V V
All clock and data inputs are compatible with the JEDEC standard to SSTL_18. The
control inputs are LVCMOS. All outputs are 1.8 V CMOS drivers that have been
optimized to drive the DDR2 DIMM load.
The SSTU32864 operates from a differential clock (CK and CK). Data are registered
at the crossing of CK going HIGH, and CK going LOW.
The C0 input controls the pinout configuration of the 1:2 pinout from A configuration
(when LOW) to B configuration (when HIGH). The C1 input controls the pinout
configuration from 25-bit 1:1 (when LOW) to 14-bit 1:2 (when HIGH).
The device supports low-power standby operation. When the reset input (RESET) is
LOW, the differential input receivers are disabled, and undriven (floating) data, clock
and reference voltage (V
registers are reset, and all outputs are forced LOW. The LVCMOS RESET and Cn
inputs must always be held at a valid logic HIGH or LOW level.
To ensure defined outputs from the register before a stable clock has been supplied,
RESET must be held in the LOW state during power-up.
In the DDR2 RDIMM application, RESET is specified to be completely asynchronous
with respect to CK and CK. Therefore, no timing relationship can be guaranteed
between the two. When entering reset, the register will be cleared and the data
outputs will be driven LOW quickly, relative to the time to disable the differential input
receivers. However, when coming out of reset, the register will become active quickly,
relative to the time to enable the differential input receivers. As long as the data inputs
are LOW, and the clock is stable during the time from the LOW-to-HIGH transition of
RESET until the input receivers are fully enabled, the design of the SSTU32864 must
ensure that the outputs will remain LOW, thus ensuring no glitches on the output.
The device monitors both DCS and CSR inputs and will gate the Qn outputs from
changing states when both DCS and CSR inputs are HIGH. If either DCS or CSR
input is LOW, the Qn outputs will function normally. The RESET input has priority over
the DCS and CSR control and will force the outputs LOW. If the DCS-control
functionality is not desired, then the CSR input can be hardwired to ground, in which
case the setup time requirement for DCS would be the same as for the other D data
inputs.
The SSTU32864 is available in the LFBGA96 package.
SSTU32864
1.8 V configurable registered buffer
for DDR2 RDIMM applications
Rev. 01 — 12 July 2004
DD
operation.
REF
) inputs are allowed. In addition, when RESET is LOW all
Objective data
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SSTU32864 Summary of contents

Page 1

... As long as the data inputs are LOW, and the clock is stable during the time from the LOW-to-HIGH transition of RESET until the input receivers are fully enabled, the design of the SSTU32864 must ensure that the outputs will remain LOW, thus ensuring no glitches on the output. ...

Page 2

... Ordering information +70 C. amb Type number Package Name Description SSTU32864EC/G LFBGA96 plastic low profile fine-pitch ball grid array package; 96 balls; body 13.5 SSTU32864EC LFBGA96 plastic low profile fine-pitch ball grid array package; 96 balls; body 13.5 9397 750 13339 Objective data 1.8 V confi ...

Page 3

... GND N D11 D22 D12 D23 GND GND R D13 D24 D14 D25 V V REF DD Rev. 01 — 12 July 2004 SSTU32864 www.DataSheet4U.com 5 6 QCKE DNU Q2 Q15 Q3 Q16 QODT DNU Q5 Q17 Q6 Q18 C1 C0 QCS DNU ZOH ZOL Q8 Q19 Q9 Q20 Q10 Q21 ...

Page 4

... D12 DNU GND GND R D13 DNU DCKE DNU V V REF DD Rev. 01 — 12 July 2004 SSTU32864 www.DataSheet4U.com 5 6 QCKEA QCKEB Q2A Q2B Q3A Q3B QODTA QODTB Q5A Q5B Q6A Q6B C1 C0 QCSA QCSB ZOH ZOL Q8A Q8B Q9A ...

Page 5

... Data outputs that will not be suspended by DCS and CSR control. No-connect. Ball present but no internal connection to the die. Do-not-use. Ball internally connected to the die which should be left open-circuit. Rev. 01 — 12 July 2004 SSTU32864 www.DataSheet4U.com Electrical characteristics ground input 1.8 V nominal 0.9 V nominal input ...

Page 6

... Fig 4. Logic diagram, 1:2 mode (positive logic). 9397 750 13339 Objective data 1.8 V configurable registered buffer for DDR2 RDIMM applications RESET REF DCKE DODT DCS CSR OTHER CHANNELS Rev. 01 — 12 July 2004 SSTU32864 www.DataSheet4U.com 1D QCKEA C1 (1) QCKEB R 1D QODTA C1 (1) QODTB R 1D QCSA C1 (1) ...

Page 7

... floating floating floating floating Rev. 01 — 12 July 2004 SSTU32864 Outputs Dn DODT, DCKE ...

Page 8

... REF 0 Data inputs, CSR V + 250 mV REF Data inputs, CSR - Data inputs, CSR V + 125 mV REF Data inputs, CSR - RESET RESET CK, CK 0.675 CK, CK 600 - - 0 Rev. 01 — 12 July 2004 SSTU32864 www.DataSheet4U.com Min Max Unit 0.5 +2.5 V [2], [3] 0.5 +2.5 V [2], [ ...

Page 9

... mA 1 250 mV 1 REF 0 600 mV; ICR 1 GND 1 Rev. 01 — 12 July 2004 SSTU32864 www.DataSheet4U.com Min Typ Max Unit 1 0 100 ...

Page 10

... DCS, CSR, ODT, CKE, and data after (max) after RESET is taken HIGH. ACT INACT = 1 amb Conditions [1] clock to output [1], clock to output reset to output = 1 Conditions Rev. 01 — 12 July 2004 SSTU32864 www.DataSheet4U.com Min Typ Max Unit - - 450 MHz [ [3] - ...

Page 11

... INPUT V ICR = 600 250 mV (AC voltage levels) for differential inputs. V REF = V 250 mV (AC voltage levels) for differential inputs. V REF Rev. 01 — 12 July 2004 SSTU32864 www.DataSheet4U.com 20%, unless otherwise 1000 350 ps, 50 OUT 1000 SEE NOTE (1) ...

Page 12

... OUTPUT and t are the same PHL 250 mV (AC voltage levels) for differential inputs. V REF = V 250 mV (AC voltage levels) for differential inputs. V REF Rev. 01 — 12 July 2004 SSTU32864 www.DataSheet4U.com V ICR REF V IL 002aaa374 = V for LVCMOS inputs GND for LVCMOS inputs ...

Page 13

... L OUTPUT dv_f DUT OUT SEE NOTE (1) includes probe and jig capacitance. L dt_r dv_r 20% OUTPUT Rev. 01 — 12 July 2004 SSTU32864 www.DataSheet4U.com 20 %, unless otherwise TEST POINT SEE NOTE (1) 002aaa377 V OH 80% 20 dt_f 002aaa378 ...

Page 14

... 13 0.1 0.8 0.15 0.1 13.4 REFERENCES JEDEC JEITA Rev. 01 — 12 July 2004 SSTU32864 www.DataSheet4U.com SOT536 detail 0.2 EUROPEAN ISSUE DATE PROJECTION 00-03-04 03-02-05 © Koninklijke Philips Electronics N.V. 2004. All rights reserved ...

Page 15

... Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. 9397 750 13339 Objective data 1.8 V configurable registered buffer for DDR2 RDIMM applications 2.5 mm Rev. 01 — 12 July 2004 SSTU32864 www.DataSheet4U.com 3 350 mm so called 3 so called small/thin packages. ...

Page 16

... Suitability of surface mount IC packages for wave and reflow soldering methods [1] [3] , LBGA, LFBGA, SQFP, [3] , TFBGA, USON, VFBGA , SO, SOJ [8] [9] [8] , PMFP , WQCCN..L Rev. 01 — 12 July 2004 SSTU32864 www.DataSheet4U.com Soldering method [2] Wave Reflow not suitable suitable [4] not suitable suitable suitable suitable [5][6] not recommended ...

Page 17

... Description 01 20040712 - Objective data (9397 750 13339) 9397 750 13339 Objective data 1.8 V configurable registered buffer for DDR2 RDIMM applications 10 C measured in the atmosphere of the reflow Rev. 01 — 12 July 2004 SSTU32864 www.DataSheet4U.com © Koninklijke Philips Electronics N.V. 2004. All rights reserved ...

Page 18

... Rev. 01 — 12 July 2004 SSTU32864 www.DataSheet4U.com Fax: + 24825 © Koninklijke Philips Electronics N.V. 2004. All rights reserved ...

Page 19

... Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Date of release: 12 July 2004 Document order number: 9397 750 13339 1.8 V configurable registered buffer for DDR2 RDIMM applications SSTU32864 www.DataSheet4U.com ...

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