PIC18F24K20-I/SS Microchip Technology, PIC18F24K20-I/SS Datasheet - Page 43
![IC PIC MCU FLASH 8KX16 28SSOP](/photos/6/81/68119/150-28-ssop_sml.jpg)
PIC18F24K20-I/SS
Manufacturer Part Number
PIC18F24K20-I/SS
Description
IC PIC MCU FLASH 8KX16 28SSOP
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets
1.PIC18F25K20T-ISS.pdf
(42 pages)
2.PIC18F25K20T-ISS.pdf
(12 pages)
3.PIC18F25K20T-ISS.pdf
(14 pages)
4.PIC18F25K20T-ISS.pdf
(456 pages)
5.PIC18F26K20-ISO.pdf
(430 pages)
Specifications of PIC18F24K20-I/SS
Program Memory Type
FLASH
Program Memory Size
16KB (8K x 16)
Package / Case
28-SSOP
Core Processor
PIC
Core Size
8-Bit
Speed
64MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
24
Eeprom Size
256 x 8
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
768 B
Interface Type
CCP/ECCP/EUSART/I2C/MSSP/SPI
Maximum Clock Frequency
64 MHz
Number Of Programmable I/os
25
Number Of Timers
4
Operating Supply Voltage
3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
11-ch x 10-bit
Package
28SSOP
Device Core
PIC
Family Name
PIC18
Maximum Speed
64 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC18F24K20-I/SS
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- PIC18F25K20T-ISS PDF datasheet
- PIC18F25K20T-ISS PDF datasheet #2
- PIC18F25K20T-ISS PDF datasheet #3
- PIC18F25K20T-ISS PDF datasheet #4
- PIC18F26K20-ISO PDF datasheet #5
- Current page: 43 of 430
- Download datasheet (7Mb)
3.0
PIC18F2XK20/4XK20 devices offer a total of seven
operating modes for more efficient power manage-
ment. These modes provide a variety of options for
selective power conservation in applications where
resources may be limited (i.e., battery-powered
devices).
There are three categories of power-managed modes:
• Run modes
• Idle modes
• Sleep mode
These categories define which portions of the device
are clocked and sometimes, what speed. The Run and
Idle modes may use any of the three available clock
sources (primary, secondary or internal oscillator
block); the Sleep mode does not use a clock source.
The power-managed modes include several power-
saving features offered on previous PIC
devices. One is the clock switching feature which allows
the controller to use the Timer1 oscillator in place of the
primary oscillator. Also included is the Sleep mode,
offered by all PIC
device clocks are stopped.
3.1
Selecting a power-managed mode requires two
decisions:
• Whether or not the CPU is to be clocked
• The selection of a clock source
The IDLEN bit of the OSCCON register controls CPU
clocking, while the SCS<1:0> bits of the OSCCON
register select the clock source. The individual modes,
bit settings, clock sources and affected modules are
summarized in Table 3-1.
TABLE 3-1:
© 2008 Microchip Technology Inc.
Sleep
PRI_RUN
SEC_RUN
RC_RUN
PRI_IDLE
SEC_IDLE
RC_IDLE
Note 1:
Mode
2:
POWER-MANAGED MODES
Selecting Power-Managed Modes
IDLEN reflects its value when the SLEEP instruction is executed.
Includes HFINTOSC and HFINTOSC postscaler, as well as the LFINTOSC source.
IDLEN
POWER-MANAGED MODES
N/A
N/A
N/A
®
0
1
1
1
OSCCON Bits
microcontroller devices, where all
(1)
SCS<1:0>
N/A
00
01
1x
00
01
1x
®
microcontroller
Clocked
Clocked
Clocked
CPU
Module Clocking
Off
Off
Off
Off
Preliminary
Peripherals
Clocked
Clocked
Clocked
Clocked
Clocked
Clocked
Off
3.1.1
The SCS<1:0> bits allow the selection of one of three
clock sources for power-managed modes. They are:
• the primary clock, as defined by the FOSC<3:0>
• the secondary clock (the Timer1 oscillator)
• the internal oscillator block
3.1.2
Switching from one power-managed mode to another
begins by loading the OSCCON register. The
SCS<1:0> bits select the clock source and determine
which Run or Idle mode is to be used. Changing these
bits causes an immediate switch to the new clock
source, assuming that it is running. The switch may
also be subject to clock transition delays. These are
discussed in Section 3.1.3 “Clock Transitions and
Status Indicators” and subsequent sections.
Entry to the power-managed Idle or Sleep modes is
triggered by the execution of a SLEEP instruction. The
actual mode that results depends on the status of the
IDLEN bit of the OSCCON register.
Depending on the current mode and the mode being
switched to, a change to a power-managed mode does
not always require setting all of these bits. Many
transitions may be done by changing the oscillator select
bits, or changing the IDLEN bit, prior to issuing a SLEEP
instruction. If the IDLEN bit is already configured
correctly, it may only be necessary to perform a SLEEP
instruction to switch to the desired mode.
PIC18F2XK20/4XK20
Configuration bits
None – All clocks are disabled
Primary – LP, XT, HS, HSPLL, RC, EC and
Internal Oscillator Block
This is the normal full power execution mode.
Secondary – Timer1 Oscillator
Internal Oscillator Block
Primary – LP, XT, HS, HSPLL, RC, EC
Secondary – Timer1 Oscillator
Internal Oscillator Block
Available Clock and Oscillator Source
CLOCK SOURCES
ENTERING POWER-MANAGED
MODES
(2)
(2)
(2)
.
DS41303D-page 41
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