PIC16F884-I/PT Microchip Technology, PIC16F884-I/PT Datasheet - Page 116

IC PIC MCU FLASH 4KX14 44TQFP

PIC16F884-I/PT

Manufacturer Part Number
PIC16F884-I/PT
Description
IC PIC MCU FLASH 4KX14 44TQFP
Manufacturer
Microchip Technology
Series
PIC® 16Fr

Specifications of PIC16F884-I/PT

Program Memory Type
FLASH
Program Memory Size
7KB (4K x 14)
Package / Case
44-TQFP, 44-VQFP
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
35
Eeprom Size
256 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 14x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC16F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
MSSP/EUSART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
35
Number Of Timers
3
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM164120-2
Minimum Operating Temperature
- 40 C
On-chip Adc
14-ch x 10-bit
Package
44TQFP
Device Core
PIC
Family Name
PIC16
Maximum Speed
20 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
XLT44PT3 - SOCKET TRAN ICE 44MQFP/TQFPAC164305 - MODULE SKT FOR PM3 44TQFP444-1001 - DEMO BOARD FOR PICMICRO MCU
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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PIC16F884-I/PT
0
PIC16F882/883/884/886/887
10.1.2
To read a data memory location, the user must write the
address to the EEADR register, clear the EEPGD
control bit of the EECON1 register, and then set control
bit RD. The data is available at the very next cycle, in
the EEDAT register; therefore, it can be read in the next
instruction. EEDAT will hold this value until another
read or until it is written to by the user (during a write
operation).
EXAMPLE 10-1:
EXAMPLE 10-2:
DS41291F-page 114
BANKSEL EEADR
MOVLW
MOVWF
BANKSEL EECON1
BCF
BSF
BANKSEL EEDAT
MOVF
BCF
BANKSEL EEADR
MOVLW
MOVWF
MOVLW
MOVWF
BANKSEL EECON1
BCF
BSF
BCF
BTFSC
GOTO
MOVLW
MOVWF
MOVLW
MOVWF
BSF
BSF
SLEEP
BCF
BCF
BCF
DATA_EE_ADDR
EEADR
EECON1, EEPGD ;Point to DATA memory
EECON1, RD
EEDAT, W
STATUS, RP1
READING THE DATA EEPROM
MEMORY
DATA_EE_ADDR
EEADR
DATA_EE_DATA
EEDAT
EECON1, EEPGD
EECON1, WREN
INTCON, GIE
INTCON, GIE
$-2
55h
EECON2
AAh
EECON2
EECON1, WR
INTCON, GIE
EECON1, WREN
STATUS, RP0
STATUS, RP1
DATA EEPROM READ
DATA EEPROM WRITE
;
;
;Data Memory
;Address to read
;
;EE Read
;
;W = EEDAT
;Bank 0
;
;
;Data Memory Address to write
;
;Data Memory Value to write
;
;Point to DATA memory
;Enable writes
;Disable INTs.
;SEE AN576
;
;Write 55h
;
;Write AAh
;Set WR bit to begin write
;Enable INTs.
;Wait for interrupt to signal write complete
;Disable writes
;Bank 0
10.1.3
To write an EEPROM data location, the user must first
write the address to the EEADR register and the data
to the EEDAT register. Then the user must follow a
specific sequence to initiate the write for each byte.
The write will not initiate if the above sequence is not
followed exactly (write 55h to EECON2, write AAh to
EECON2, then set WR bit) for each byte. Interrupts
should be disabled during this code segment.
Additionally, the WREN bit in EECON1 must be set to
enable write. This mechanism prevents accidental
writes to data EEPROM due to errant (unexpected)
code execution (i.e., lost programs). The user should
keep the WREN bit clear at all times, except when
updating EEPROM. The WREN bit is not cleared
by hardware.
After a write sequence has been initiated, clearing the
WREN bit will not affect this write cycle. The WR bit will
be inhibited from being set unless the WREN bit is set.
At the completion of the write cycle, the WR bit is
cleared in hardware and the EE Write Complete
Interrupt Flag bit (EEIF) is set. The user can either
enable this interrupt or poll this bit. EEIF must be
cleared by software.
WRITING TO THE DATA EEPROM
MEMORY
© 2009 Microchip Technology Inc.

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